ht82a836r Holtek Semiconductor Inc., ht82a836r Datasheet - Page 40

• Manufacturer Part Number: ht82a836r
• Description: Usb Audio Mcu
• Manufacturer: Holtek Semiconductor Inc.

MISC Register
The MISC register combines command and status to
control the desired endpoint FIFO action and to show
the status of the desired endpoint FIFO. The MISC reg-
ister will be cleared by a USB reset signal.
Further explanation of each of the bits is given below:
Rev. 1.00
CRCF
The CRCF read/write is an error condition failure flag
that includes CRC, PID and no integrate token error.
CRCF will be set by the hardware but needs to be
cleared by the firmware.
EOT
The EOT read only read only flag is the Token Pack-
age active flag. Note that this flag is active low.
NMI
The read/write NMI bit is the NAK token interrupt
mask flag. If this bit set, when the device sends a NAK
token to the host, the interrupt will be disabled. Other-
wise if this bit is cleared, when the device sends a
NAK token to the host, it will enter the interrupt sub-
routine.
REQUEST
The read/write REQUEST, if set high, can request the
FIFO after the corresponding status has been set.
When finished this bit must be set low.
TX
The read/write TX bit represents the direction and
MCU access transition end. When set high, the MCU
Miscellaneous Register - MISC
40
desires to write data to the FIFO. After finishing, this
bit must be set low before terminating the request to
represent a transition end. For an MCU read opera-
tion, this bit must be set low and then high after finish-
ing.
CLEAR
The read/write CLEAR bit MCU is used to request a
FIFO clear, even if the FIFO is not ready. After clearing
the FIFO, the USB interface will send a force_tx_err to
tell the Host that data under-run if the Host wants to
read data.
ISO_IN_EN
The read/write ISO_IN_EN bit enables the
isochronous in pipe interrupt.
ISO_OUT_EN
The read/write ISO_OUT_EN bit enables the
isochronous out pipe interrupt.
SETCMD
The read/write SETCMD bit is used to show that the
data in the FIFO is a setup command. The bit will re-
main in the same state until the following data enters
the FIFO.
READY
The read only READY bit is used to indicate that the
desired FIFO is ready.
LEN0
The read only LEN0 bit is used to indicate that the host
has sent a 0-sized packet to the MCU. This bit must be
cleared by a read action to the corresponding FIFO.
HT82A836R
March 20, 2008