wm9081 Wolfson Microelectronics plc, wm9081 Datasheet - Page 66

• Manufacturer Part Number: wm9081
• Description: Mono Dac With 2.6w Class Ab/d Speaker Driver, Dynamic Range Controller And Retune Mobile Parametric Equalizer
• Manufacturer: Wolfson Microelectronics plc

WM9081
Figure 53 WM9081 Clocking Overview
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CLK_SYS CONTROL
The CLK_SRC_SEL bit is used to select the source for CLK_SYS. The source can be either MCLK
or the FLL output. The selected source may also be adjusted by the MCLKDIV2 divider to generate
CLK_SYS. These register fields are described in Table 37. See “Frequency Locked Loop (FLL)” for
more details of the Frequency Locked Loop clock generator.
The CLK_SYS signal is enabled by register bit CLK_SYS_ENA. This bit should be set to 0 when
reconfiguring clock sources or when no clock source is present. It is not recommended to change
MCLK_SRC or CLK_SRC_SEL while the CLK_SYS_ENA bit is set.
The core clocking requirements are configured by setting the SAMPLE_RATE and CLK_SYS_RATE
fields as described in Table 37. The WM9081 supports DAC sample rates (fs) from 8kHz up to
96kHz. The CLK_SYS_RATE field must be set according to the ratio of CLK_SYS to fs.
The DSP / DAC clock function is enabled by register bit CLK_DSP_ENA.
R12 (0Ch)
Clock
Control1
REGISTER
ADDRESS
BIT
7
MCLKDIV2
LABEL
DEFAULT
0
MCLK Divider
0 = MCLK
1 = MCLK / 2
DESCRIPTION
PP, Rev 3.0, April 2009
Pre-Production
66