wm9081 Wolfson Microelectronics plc, wm9081 Datasheet - Page 23

• Manufacturer Part Number: wm9081
• Description: Mono Dac With 2.6w Class Ab/d Speaker Driver, Dynamic Range Controller And Retune Mobile Parametric Equalizer
• Manufacturer: Wolfson Microelectronics plc

Pre-Production
Figure 17 Multiple Register Read from Last Address using Auto-increment
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Multiple Write and Multiple Read operations enable the host processor to access sequential blocks of
the data in the WM9081 register map faster than is possible with single register operations. The
auto-increment option is enabled when the AUTO_INC register bit is set. This bit is defined in Table
5. Auto-increment is enabled by default.
SMBUS Alert Response Address protocol is supported by the WM9081 when the ARA_ENA register
bit is set. This function enables a bus controller to poll multiple devices on the I2C bus
simultaneously in order to respond to Interrupt events efficiently. The WM9081 does not support
automatic clearing of the SMBALERT# (implemented as IRQ on this device); a host device must
service the alert and manually clear the IRQ status before proceeding to any other alerting devices in
the system. The WM9081 device address used by this protocol is set as described in Table 5.
R40 (28h) MW
Slave 1
Table 5 Auto-Increment and Alert Response Address Control
3-WIRE CONTROL MODE
The WM9081 is controlled by writing to registers through a 3-wire serial control interface. A control
word consists of 24 bits. The first bit is the read/write bit (R/W), which is followed by 7 address bits
(A6 to A0) that determine which control register is accessed. The remaining 16 bits (B15 to B0) are
data bits, corresponding to the 16 bits in each control register.
In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on
CS
In Write operations (R/W=0), all SDIN bits are driven by the controlling device.
In Read operations (R/W=1), the SDIN pin is driven by the controlling device to clock in the register
address, after which the WM9081 drives the SDIN pin to output the applicable data bits.
The 3-wire control mode timing is illustrated in Figure 18.
Figure 18 3-Wire Serial Control Interface
¯ ¯ latches in a complete control word consisting of the last 24 bits.
ADDRESS
BIT
3
1
ARA_ENA
AUTO_INC
LABEL
DEFAULT
0
1
Alert Response Address protocol enable
0 = Disabled
1 = Enabled
Enable Auto-Increment function
0 = Disabled
1 = Enabled
DESCRIPTION
PP, Rev 3.0, April 2009
WM9081
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