xrt75r12 Exar Corporation, xrt75r12 Datasheet - Page 51

• Manufacturer Part Number: xrt75r12
• Description: Twelve Channel E3/ds3/sts-1 Line Interface Unit With Jitter
• Manufacturer: Exar Corporation

REV. 1.0.4
N
F
7.3
OTE
IGURE
S
YMBOL
NA
NA
: 1. This timing parameter is based on the frequency of the synchronous clock (PCLK). To determine the access
t
t
t
t
t
0
1
2
3
4
Addr[7:0]
A
time, use the following formula: (PCLK
PCLK
36. S
RDY
D[7:0]
WR
Register Map
DDRESS
RD
(H
0x00
0x01
0x02
CS
EX
)
Valid Address to CS Falling Edge
CS Falling Edge to RD Assert
RD Assert to RDY Assert
RD Pulse Width (t
CS Falling Edge to WR Assert
WR Assert to RDY Assert
WR Pulse Width (t
PCLK Period
PCLK Duty Cycle
PCLK "High/Low" time
YNCHRONOUS
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
t
0
T
ABLE
C
t
1
OMMAND
17: C
µP I
(D
2
4
)
)
ECIMAL
T
CR0
CR1
CR2
P
NTERFACE
ABLE
Valid Address
OMMAND
READ OPERATION
ARAMETER
R
t
EGISTER
2
)
16: S
C
R
HANNEL
S
period
Valid Data for Readback
YNCHRONOUS
EGISTER
IGNALS
L
APST
IER0
ISR0
* 2) + 5ns
ABEL
0 C
D
A
ONTROL
URING
DDRESS
48
T
RUR
R/W
R/W
T
YPE
IMING
P
R
ROGRAMMED
EGISTERS
M
0
0
-
40
0
-
40
15
t
AP
0
APS Transmit Redundancy Control Register 0-5
Source Level Interrupt Enable Register - Ch 0
Source Level Interrupt Status Register Ch 0
S
PECIFICATIONS
,
WITHIN THE
M
t
3
IN
I/O R
Data Available to Write Into the LIU
WRITE OPERATION
-
-
35
-
-
35
-
XRT75R12
EAD AND
t
R
4
EGISTER
Valid Address
M
AX
W
N
AME
RITE
ns
ns
ns, see note 1
ns
ns
ns, see note 1
ns
ns
XRT75R12
O
PERATIONS
U
NITS