xrt75r12 Exar Corporation, xrt75r12 Datasheet
xrt75r12
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xrt75r12 Summary of contents
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... TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER OCTOBER 2007 GENERAL DESCRIPTION The XRT75R12 is a twelve channel fully integrated Line Interface Unit (LIU) featuring EXAR’s R Technology (Reconfigurable, Relayless Redundancy) for E3/DS3/STS-1 applications. The LIU incorporates 12 independent Receivers, Transmitters and Jitter Attenuators in a single 420 Lead TBGA package ...
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... XRT75R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR FEATURES RECEIVER 3 R Technology (Reconfigurable, Redundancy) On chip Clock and Data Recovery circuit for high input jitter tolerance Meets E3/DS3/STS-1 Jitter Tolerance Requirement Detects and Clears LOS as per G.775 Receiver Monitor mode handles flat ...
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... C T LEARANCE HRESHOLDS FOR A GIVEN SETTING OF E3 ITU-T G.775 .................................................................................................. 23 AS PER E3 ITU-T G.775................................................................................................... 24 AS PER S DS3/STS-1 ...................................................................................................... FOR S E3. ................................................................................................................... FOR ................................................................................................................................. 25 ........................................................................................................ 25 ...................................................................................................................................... 27 XRT75R12 ( DUAL T ............................................................................................................................... 28 IMING ( NCODER AND ECODER ARE NABLED I XRT75R12 ............................................ 19 ICROPROCESSOR REQEN (DS3 STS-1 A AND - ) .............................................. 27 RAIL DATA ) ...
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... MICROPROCESSOR INTERFACE BLOCK ........................................................................................ ABLE ELECTING THE ICROPROCESSOR F 34 IGURE IMPLIFIED LOCK IAGRAM OF THE 7.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ......................................................................... 45 T 14: XRT75R12 M ABLE ICROPROCESSOR 7.2 ASYNCHRONOUS AND SYNCHRONOUS DESCRIPTION .......................................................................... 46 F 35. A µP I IGURE SYNCHRONOUS NTERFACE T 15 ABLE SYNCHRONOUS IMING PECIFICATIONS F 36 ...
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... T 38 ABLE ECEIVE ONTROL EGISTER T 39: XRT75R12 R MAP ABLE EGISTER SHOWING T 40 ABLE HANNEL ONTROL EGISTER T 41: XRT75R12 R MAP ABLE EGISTER SHOWING T 42 ABLE ITTER TTENUATOR ONTROL T 43: XRT75R12 R MAP ABLE EGISTER SHOWING T 44 MSB R ABLE ...
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... Transmit Clock Input These input pins have three functions: • They function as the timing source for the Transmit Section of the corresponding channel within the XRT75R12. • They are used by the Transmit Section of the LIU IC to sample the corresponding TxPOS_n and TxNEG_n input pins. ...
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... Transmit TTIP Output - Positive Polarity Signal These output pins along with the corresponding TRING_n output pins, function as the Transmit DS3/E3/STS-1 Line output signal drivers for a given channel of the XRT75R12. Connect this signal and the corresponding TRING_n output signal to a 1:1 transformer. ...
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... XRT75R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR SYSTEM-SIDE TRANSMIT INPUT AND TRANSMIT CONTROL PINS IGNAL AME YPE C23 MTip0 AD23 MTip1 D19 MTip2 AC19 MTip3 D15 MTip4 AC15 MTip5 E11 MTip6 AB11 MTip7 E8 MTip8 AB8 MTip9 ...
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... The data output via this pin is updated upon the active edge of RxCLK_n output clock signal. Single-Rail Mode - Receive Data Output In the Single-Rail Mode, all Receive (or Recovered) data will be output via this pin. The data output via this pin is updated upon the active edge of RxCLK_n output clock signal. 6 XRT75R12 ...
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... RxCLK11 D ESCRIPTION Receive Negative Data Output/Line Code Violation The function of these pins depends on whether the XRT75R12 is configured in Single Rail or Dual Rail mode. Dual-Rail Mode - Receive Negative Polarity Data Output In the Dual-Rail Mode, all negative-polarity data will be output via this pin. The positive-polarity data will be output via the corresponding RxPOS_n output pin ...
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... ESCRIPTION Receive TIP Input These input pins along with the corresponding RRing_n input pin function as the Receive DS3/E3/STS-1 Line input signal for a given channel of the XRT75R12. Cconnect this signal and the corresponding RRING_n input signal to a 1:1 transformer. Whenever the RTIP/RRING input pins are receiving a positive-polarity pulse within the incoming DS3 STS-1 line signal, this input pin will be pulsed to a higher voltage than its corresponding RRING_n input pin ...
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... CLKOUT11 D ESCRIPTION Single Frequency Mode Enable This input pin is used to configure the XRT75R12 to operate in the SFM (Single Frequency Mode). When this feature is invoked, the SFM Synthesizer will become active. By applying a 12.288MHz clock signal to the STS-1Clk/12M pin, the XRT75R12 will generate all of the appropriate clock signals (e.g., 34.368MHz, 44.736MHz or 51 ...
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... This pin controls the Microprocessor Parallel Interface mode. "High" sets a Synchronous clocked interface mode with a clock from the Host. "Low" sets an Asynchronous mode where a clock internal to the XRT75R12 will time the operations. High speed clock supplied by the Host to provide timing in the Synchronous Interface mode ...
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... This pin will remain "Low" until the Interrupt has been serviced. 2. This pin must be pulled "High" with a 3k RESET Input Pulsing this input "Low" causes the XRT75R12 to reset the contents of the on- chip Command Registers to their default values consequence, the XRT75R12 will then also be operating in its default condition. ...
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... DVDD should be isolated from the analog power supplies. For best results, use an internal power plane for isolation internal power plane is not available, a ferrite bead can be used. Every two DVDD power supply pins should be bypassed to ground through at least one 0.1 F capacitor. 12 XRT75R12 ...
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... XRT75R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR GROUND PINS AME IN UMBERS RGND0 A22 RGND1 AF22 RGND2 A18 RGND3 AF18 RGND4 E14 RGND5 AB14 RGND6 E13 RGND7 AB13 RGND8 D9 RGND9 AC9 RGND10 A5 RGND11 AF5 TGND0 A23 TGND1 ...
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... TTip8 D15 MTip4 AGND D16 DGND RRing8 D17 AGND AGND D18 RVDD2 TTip6 D19 MTip2 DVDD D20 DGND RRing6 D21 AGND DVDD D22 RVDD0 14 XRT75R12 AME D23 MRing0 D24 DGND D25 RLOS0 D26 DVDD E1 DGND E2 RxPOS10 E3 RxCLK10 E4 TxPOS10 E5 AGND ...
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... XRT75R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR AME IN F5 TxCLK10 J25 F22 TxCLK0 J26 F23 RxNEG/LCV0 K1 F24 RxNEG/LCV2 K2 F25 DVDD K3 F26 DGND K4 G1 TxCLK6 K5 G2 TxPOS6 K22 G3 RxPOS8 K23 G4 RLOS8 K24 G5 RLOL10 K25 G22 RLOL0 ...
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... DGND AD24 TRing1 AGND AD25 RLOS1 RVDD3 AD26 RxPOS1 MTip3 AE1 AGND DGND AE2 TDO AGND AE3 TRing11 RVDD1 AE4 TVDD11 16 XRT75R12 AME IN IN AME AE5 RTip11 AE6 TGND9 AE7 TRing9 AE8 DGND AE9 RTip9 AE10 TVDD7 AE11 TRing7 AE12 ...
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... XRT75R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR AME AF13 AVDD AF14 RTip5 AF15 TGND5 AF16 DVDD AF17 DVDD AF18 RGND3 AF19 TGND3 AF20 DVDD AF21 DVDD AF22 RGND1 AF23 TGND1 AF24 DVDD AF25 AGND AF26 AGND 17 REV ...
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... TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR REV. 1.0.4 FUNCTIONAL DESCRIPTION The XRT75R12 is a twelve channel fully integrated Line Interface Unit featuring EXAR’s R (Reconfigurable, Relayless Redundancy) for E3/DS3/STS-1 applications. independent Receivers, Transmitters and Jitter Attenuators in a single 420 Lead TBGA package. Each channel can be independently programmed to support E3, DS-3 or STS-1 line rates using one input clock reference of 12 ...
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... XRT75R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR 2.0 CLOCK SYNTHESIZER The LIU uses a flexible user interface for accepting clock references to generate the internal master clocks used to drive the LIU. The reference clock used to supply the microprocessor timing is generated from the DS SFM clock input ...
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... E3 only, then the DS3Clk input pin may be hard wire connected to the E3Clk input pin IGURE LOCK ISTRIBUTION ONGIFURED IN DS3Clk E3Clk N : For one input clock reference, the single frequency mode should be used. OTE SFM ODE ITHOUT SING CLKOUT_n Clock Synthesizer LOL_n Processor 20 XRT75R12 ...
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... XRT75R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR 3.0 THE RECEIVER SECTION The receiver is designed so that the LIU can recover clock and data from an attenuated line signal caused by cable loss or flat loss according to industry specifications. Once data is recovered processed and presented at the receiver outputs according to the format chosen to interface with a Framer/Mapper or ASIC ...
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... ALOS condition is reflected in the ALOS_n status control register. RLOS is the logical OR of the DLOS and ALOS states. When the RLOS condition occurs the RLOS_n output pin is toggled “High” and the RLOS_n bit is set to “1” in the status control register. D IAGRAM Peak Detector Slicer AGC/ Equalizer LOS Detector 22 XRT75R12 ...
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... XRT75R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR ALOS (A LOS) D ABLE HE NALOG REQEN (DS3 A REQEN S PPLICATION ETTING DS3 0 1 STS 3.5.2 Disabling ALOS/DLOS Detection For debugging purposes it is useful to disable the ALOS and/or DLOS detection. Writing a “1” to both ALOSDIS_n and DLOSDIS_n bits disables the LOS detection on a per channel basis ...
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... DS3 DS3/STS-1 EST ET UP FOR Attenuator ∑ Cable Simulator T S E3. EST ET UP FOR Attenuator 1 Attenuator 2 ∑ Cable Simulator 24 XRT75R12 10 UI 255 G.775 Compliance DUT XRT75R12 Test Equipment DUT XRT75R12 Test Equipment ...
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... XRT75R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR T ABLE M C ODE ABLE E3 DS3 STS-1 3.5.5 Muting the Recovered Data with LOS condition: When the LOS condition is declared, the clock recovery circuit locks into the reference clock applied to the internal master clock outputs this clock onto the RxClk_n output pin. The data on the RxPOS_n and RxNEG_n pins can be forced to zero by setting the LOSMUT_n bits in the individual channel control register to “ ...
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... Whenever the input signal violates the B3ZS or HDB3 coding sequence for bipolar violation or contains three (for B3ZS) or four (for HDB3) or more consecutive zeros, an active “High” pulse is generated on the RLCV_n output pins to indicate line code violation. MIN TYP 45 50 34.368 44.736 51. 2.5 26 XRT75R12 MAX UNITS 55 % MHz MHz MHz ...
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... Equipment (E3/DS3 or STS-1 Framer) Figure 13. D IAGRAM Tx Jitter Timing Pulse Attenuator Control Shaping Tx Control Figure 14. TxPOS TPData Transmit TxNEG TNData Logic Block TxLineClk TxClk Exar E3/DS3/STS-1 LIU 27 REV. 1.0.4 TxClk_n HDB3/ TxPOS_n B3ZS MUX Encoder TxNEG_n TxON Channel n XRT75R12 ( - ) DUAL RAIL DATA ...
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... NRZ D IGURE INGLE AIL OR Data 0 TPData TxClk 15 RANSMITTER ERMINAL NPUT t FTX t t TSU THO ATA ORMAT NCODER AND ECODER ARE XRT75R12 T IMING MIN TYP MAX UNITS 34.368 MHz 44.736 MHz 51.84 MHz NABLED 0 ...
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... XRT75R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR F 17 IGURE UAL AIL ATA ORMAT Data 0 TPData TNData TxClk 4.2 Transmit Clock The Transmit Clock applied via TxClk_n pins, for the selected data rate (for E3 = 34.368 MHz, DS3 = 44.736 MHz or STS ...
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... DSX3 or STSX-1 is greater than 225 feet, disable the Transmit Build Out Circuit EST IRCUIT R1 TTIP(n) TPData(n) 31.6 +1% TNData(n) R2 TxClk(n) TRing(n) 31 XRT75R12 Figure 20 1:1 ...
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... TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR 4.5 E3 line side parameters The XRT75R12 line output at the transformer output meets the pulse shape specified in ITU-T G.703 for 34.368 Mbits/s operation. The pulse mask as specified in ITU-T G.703 for 34.368 Mbits/s is shown in Figure 21 ...
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... Signal level to Declare Loss of Signal Signal Level to Clear Loss of Signal Occurence of LOS to LOS Declaration Time Termination of LOS to LOS Clearance Time N : The above values are OTE 0.90 0.95 12.5 R ECEIVER LINE SIDE INPUT CHARACTERISTICS 0. and V = 3.3 V± 5 XRT75R12 MIN TYP MAX UNITS 1.00 1. 1.00 1.05 14.55 16.5 ns 0.02 0. ...
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... XRT75R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR F 22. B GR-253 CORE T IGURE ELLCORE 1.2 1 0.8 0.6 0.4 0 IME IN NIT NTERVALS < < -0.85 T -0.38 < < -0.38 T 0.36 < < 0.36 T 1.4 < < -0.85 T -0.68 < < -0.68 T 0.26 < < 0. RANSMIT UTPUT ULSE EMPLATE FOR ST S-1 Pulse T emplate Time STS-1 P ...
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... IDE UTPUT AND ECEIVER INE 0.65 0.90 0.90 R ECEIVER LINE SIDE INPUT CHARACTERISTICS 0. and V = 3.3 V ± 5 DS3 B EMPLATE FOR AS PER ELLCORE DS3 Pulse T emplate Tim XRT75R12 (GR-253) IDE NPUT PECIFICATIONS NITS 0.75 0. 1.00 1. 8.6 9.65 10.6 ns 1.00 1.10 0.02 0.05 UI ...
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... XRT75R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR IME IN NIT NTERVALS < < -0.85 T -0.36 < < -0.36 T 0.36 < < 0.36 T 1.4 < < -0.85 T -0.68 < < -0.68 T 0.36 < < 0. DS3 T L ABLE RANSMITTER INE P ARAMETER T RANSMITTER LINE SIDE OUTPUT CHARACTERISTICS Transmit Output Pulse Amplitude (measured with TxLEV = 0) ...
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... This feature provides support for Redundancy the XRT75R12 is configured in Host mode, to permit a system designed for redundancy to quickly shut-off the defective line card and turn on the back-up line card, writing a “1” to the TxON_n control bits transfers the control to TxON pin. ...
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... Bellcore GR-499 CORE specifies the minimum requirement of jitter tolerance for Category I and Category II. The jitter tolerance requirement for Category II is the most stringent. as per GR-499 specification. Figure 25, jitter is introduced by the sinusoidal Data DUT XRT75R12 Clock Figure 26 37 REV. 1.0.4 Error Detector shows the jitter tolerance curve ...
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... E3/DS3/STS-1 compliant component must tolerate. versus the modulation frequency for various standards. F DS3/STS 0 JITTER FREQUENCY (kHz) Table 10 38 XRT75R12 GR-253 STS-1 GR-499 Cat II GR-499 Cat I XRT75R12 20 100 ITU-T G.823 XRT75R12 800 below shows the jitter amplitude ...
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... Jitter Attenuator An advanced crystal-less jitter attenuator per channel is included in the XRT75R12. The jitter attenuator requires no external crystal nor high-frequency reference clock. By clearing or setting the JATx/Rx_n bits in the channel control registers selects the jitter attenuator either in the Receive or Transmit path on per channel basis ...
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... KBITS G.823 34368 ETSI-TBR-24 44736 GR-499, Cat I GR-499, Cat II GR-253 CORE 51840 GR-253 CORE The jitter attenuator within the XRT75R12 meets the latest jitter attenuation specifications and/or jitter transfer characteristics as shown in the Figure F 28 IGURE ITTER RANSFER EQUIREMENTS AND A 1 ...
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... Any subsequent single bit error insertion must be done by first writing a “0” to INSPRBS bit and followed by a “1”. Figure 29 shows the status of RNEG/LCV pin when the XRT75R12 is configured in PRBS mode PRBS mode, the device is forced to operate in Single-Rail Mode. ...
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... TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR REV. 1.0.4 6.2 LOOPBACKS The XRT75R12 offers three loopback modes for diagnostic purposes. The loopback modes are selected via the RLB_n and LLB_n bits n the Channel control registers select the loopback modes. 6.2.1 ANALOG LOOPBACK ...
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... XRT75R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR 6.2.2 DIGITAL LOOPBACK When the Digital Loopback is selected, the transmit clock TxClk_n and transmit data inputs (TxPOS_n & TxNEG_n are looped back and output onto the RxClk_n, RxPOS_n and RxNEG_n pins as shown in Figure 31 ...
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... TAOS does not operate in Analog loopback or Remote loopback modes, however will function in Digital loopback mode (TAOS) IGURE RANSMIT LL NES TxCLK HDB3/B3ZS TxPOS ENCODER TxNEG RxCLK HDB3/B3ZS RxPOS DECODER RxNEG TIMING Tx CONTROL TAOS DATA & CLOCK Rx RECOVERY 44 XRT75R12 TTIP Transmit All 1's TRing RTIP RRing ...
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... MICROPROCESSOR INTERFACE BLOCK The Microprocessor Interface section supports communication between the local microprocessor (µP) and the LIU. The XRT75R12 supports a parallel interface asynchronously or synchronously timed to the LIU. The microprocessor interface is selected by the state of the Pmode input pin. Selecting the microprocessor interface mode is shown in Table 13 ...
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... AME YPE CS I Chip Select Input This active low signal selects the microprocessor interface of the XRT75R12 LIU and enables Read/Write operations with the on-chip register locations Read Signal This active low input functions as the read signal from the local pin is pulled “Low” ( “Low”) the LIU is informed that a read operation has been requested and begins the process of the read cycle ...
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... XRT75R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR 5. After the µP toggles the Write signal "Low", the LIU will toggle the RDY output pin "Low". The LIU does this to inform the µP that the data has been written into the internal register location, and that it is ready for the next command. 6. The CS input pin must be pulled " ...
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... Source Level Interrupt Enable Register - Ch 0 ISR0 RUR Source Level Interrupt Status Register XRT75R12 I EAD AND RITE PERATIONS WRITE OPERATION Valid Address Data Available to Write Into the LIU NITS - ns, see note ns, see note XRT75R12 R N EGISTER AME ...
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... Transmit Control Register - Ch 1 RC1 R/W Receive Control Register - Ch 1 CC1 R/W Channel Control Register - Ch 1 JA1 R/W Jitter Attenuator Control Register - Ch 1 EM1 R/W Error counter MSByte Ch 1 EL1 R/W Error counter LSbyte EH1 R/W Error counter Holding register HANNEL ONTROL EGISTERS 49 REV. 1.0.4 XRT75R12 R N EGISTER AME ...
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... Alarm Status Register - Ch 3 TC3 R/W Transmit Control Register - Ch 3 RC3 R/W Receive Control Register - Ch 3 CC3 R/W Channel Control Register - Ch 3 JA3 R/W Jitter Attenuator Control Register - Ch 3 EM3 R/W Error counter MSByte Ch 3 EL3 R/W Error counter LSbyte EH3 R/W Error counter Holding register 50 XRT75R12 XRT75R12 R N EGISTER AME ...
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... Alarm Status Register - Ch 5 TC5 R/W Transmit Control Register - Ch 5 RC5 R/W Receive Control Register - Ch 5 CC5 R/W Channel Control Register - Ch 5 JA5 R/W Jitter Attenuator Control Register - Ch 5 EM5 R/W Error counter MSByte Ch 5 EL5 R/W Error counter LSbyte EH5 R/W Error counter Holding register 51 REV. 1.0.4 XRT75R12 R N EGISTER AME ...
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... EGISTER DDRESS AP WITHIN THE L T ABEL YPE ) CIE R/W Channel 0-5 Interrupt Enable flags CIS R/O Channel 0-5 Interrupt status flags PN R/O Device Part Number Register VN R/O Chip Revision Number Register 52 XRT75R12 XRT75R12 R N EGISTER AME ...
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... Source Level Interrupt Enable Register - Ch 7 ISR7 RUR Source Level Interrupt Status Register - Ch 7 AS7 R/O Alarm Status Register - Ch 7 TC7 R/W Transmit Control Register - Ch 7 RC7 R/W Receive Control Register - Ch 7 CC7 R/W Channel Control Register - Ch 7 JA7 R/W Jitter Attenuator Control Register - REV. 1.0.4 XRT75R12 R N EGISTER AME ...
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... Source Level Interrupt Enable Register - Ch 9 ISR9 RUR Source Level Interrupt Status Register - Ch 9 AS9 R/O Alarm Status Register - Ch 9 TC9 R/W Transmit Control Register - Ch 9 RC9 R/W Receive Control Register - Ch 9 CC9 R/W Channel Control Register - Ch 9 JA9 R/W Jitter Attenuator Control Register - XRT75R12 XRT75R12 R N EGISTER AME ...
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... Error counter Holding register HANNEL ONTROL EGISTERS IER11 R/W Source Level Interrupt Enable Register - Ch 11 ISR11 RUR Source Level Interrupt Status Register - Ch 11 AS11 R/O Alarm Status Register - Ch 11 TC11 R/W Transmit Control Register - Ch 11 RC11 R/W Receive Control Register - REV. 1.0.4 XRT75R12 R N EGISTER AME ...
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... YPE ) CC11 R/W Channel Control Register - Ch 11 JA11 R/W Jitter Attenuator Control Register - Ch 11 EM11 R/W Error counter MSByte Ch 11 EL11 R/W Error counter LSbyte EH11 R/W Error counter Holding register CIE R/W Channel 6-11 Interrupt enable flags CIS R/O Channel 6-11 Interrupt status flags 56 XRT75R12 XRT75R12 R N EGISTER AME ...
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... THE GLOBAL/CHIP-LEVEL REGISTERS The register set, within the XRT75R12 contains ten global or chip-level registers. These registers control operations in more than one channel or apply to the complete chip. This section will present detailed information on the Global Registers. T 18: L ABLE ...
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... The master TxON control pin(pin # P4) must high state (logic 1) for this operation to turn on any channel CR8 (A ECIEVE ONTROL EGISTER RxON Ch 4 RxON Ch 3 RxON Ch 2 R/W R/W D ESCRIPTION 58 XRT75R12 00) DDRESS OCATION TxON Ch 2 TxON Ch 1 TxON Ch 0 R/W R/W R ...
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... XRT75R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR T 21: APS/R ABLE EDUNDANCY Reserved Reserved TxON AME YPE N UMBER 7,6 Reserved 5 TxON Ch 11 R/W Transmit Section ON - Channel n TxON This READ/WRITE bit-field is used to turn on or turn off the Transmit Driver associated TxON Ch 9 with Channel n ...
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... Interrupt Enable register (IERn) for the channel will activate the INT pin to the Host Disables all Channel n related Interrupts Enables Channel n-related Interrupts. The user must enable individual Channel n related Interrupts at the source level, before they are can generate an interrupt. 60 XRT75R12 60) DDRESS OCATION X ...
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... YPE R/O Channel n Interrupt Status Bit: This READ-ONLY bit-field indicates whether the XRT75R12 has a pending Channel n-related interrupt that is awaiting service. The first six channels are serviced through this location and the other six at address 0xE1. These two registers are used by the Host to identify the source channel of an active interrupt ...
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... Interrupt Enable register (IERn) for the channel will activate the INT pin to the Host Disables all Channel n related Interrupts Enables Channel n-related Interrupts. The user must enable individual Channel n related Interrupts at the source level, before they are can generate an interrupt. 62 XRT75R12 E0) DDRESS OCATION X ...
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... YPE R/O Channel n Interrupt Status Bit: This READ-ONLY bit-field indicates whether the XRT75R12 has a pending Channel n-related interrupt that is awaiting service. The last six channels are serviced through this location and the other six at address 0x61. These two registers are used by the Host to identify the source channel of an active interrupt ...
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... Chip Revision Number Value: This READ-ONLY register contains a value that represents the current revision of this XRT75R12. This revision number will always be in the form of "0x0#", where "#" hexadeci- mal value that specifies the current revision of the chip. ...
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... XRT75R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR THE PER-CHANNEL REGISTERS The XRT75R12 consists of 120 per-Channel Registers (12 channels and 10 registers per channel). presents the overall Register Map with the Per-Channel Registers unshaded. REGISTER DESCRIPTION - PER CHANNEL REGISTERS T 29: XRT75R12 R ...
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... Change of FL (FIFO Limit Alarm) Condition Interrupt Enable - Ch n: This READ/WRITE bit-field is used to enable or disable the Change of FIFO Limit Alarm Condition Interrupt. If the user enables this interrupt, the XRT75R12 will generate an interrupt if any of the following events occur. • Whenever the Jitter Attenuator (within Channel n) declares the FL (FIFO Limit Alarm) condition. • ...
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... Enable - Ch 0: This READ/WRITE bit-field is used to enable or disable the Change of the Receive LOS Defect Condition Interrupt. If the user enables this interrupt, then the XRT75R12 will generate an interrupt any time any of the following events occur. • Whenever the Receive Section (within Channel n) declares the LOS Defect Condition. • ...
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... Indicates that the Change of the Transmit DMO Condition Interrupt has occurred since the last read of this register The user can determine the current state of the Transmit DMO OTE Condition by reading out the contents of Bit 0 (Transmit DMO Condition) within the Alarm Status Register.(n) 68 XRT75R12 DDRESS OCATION XM ...
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... XRT75R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR T 33: XRT75R12 R ABLE Reserved Loss of PRBS Digital LOS Pattern Sync Defect Declared R/O R ABLE LARM UMBER AME 7 Reserved 6 Loss of PRBS Pat- tern Lock MAP ...
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... Defect condition OTES 1. LOS Detection (within each channel of the XRT75R12) is performed by both an Analog LOS Detector and a Digital LOS Detector. The LOS state of a given Channel is simply a WIRED the LOS Defect Declare states of these two detectors. 2. The current LOS Defect Condition (for the channel) can be determined by reading out the contents of Bit 1 (Receive LOS Defect Declared) within this register ...
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... XRT75R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR T 34 ABLE LARM UMBER AME 3 FL Alarm Declared 2 Receive LOL Condi- tion Declared TATUS EGISTER HANNEL DDRESS (n = [0:11] & = 0-5 & 8- YPE R/O FL (FIFO Limit) Alarm Declared: This READ-ONLY bit-field indicates whether or not the Jitter Attenuator block (within Channel_n) is currently declaring the FIFO Limit Alarm ...
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... The Transmit Section will clear the Transmit DMO Alarm condition upon detecting bipolar activity on the Transmit Output Line signal Indicates that the Transmit Section of Channel_n is NOT currently declaring the Transmit DMO Alarm condition Indicates that the Transmit Section of Channel_n is currently declaring the Transmit DMO Alarm condition. 72 XRT75R12 OCATION XM ESCRIPTION ...
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... XRT75R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR T 35: XRT75R12 R ABLE Reserved Internal Transmit Drive Monitor R/W T 36: T ABLE RANSMIT UMBER AME Reserved 5 Internal Transmit R/W Drive Monitor Enable 4 Insert PRBS Error R/W 3 Reserved MAP ...
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... Section (of Channel_n) will always generate a DS3 pulse that complies with the Isolated Pulse Template requirements per Bellcore GR-499-CORE STS-1 pulse that complies with the Pulse Template requirements per Tel- cordia GR-253-CORE This bit-field is ignored if the channel has been configured to operate OTE in the E3 Mode. 74 XRT75R12 OCATION XM ESCRIPTION ...
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... XRT75R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR T 37: XRT75R12 R ABLE Reserved Disable DLOS Detector R ABLE ECEIVE UMBER AME Reserved 5 Disable DLOS R/W Detector 4 Disable ALOS R/W Detector 3 RxCLKINV R/W MAP R C EGISTER ...
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... Disables the Receive Equalizer within the corresponding channel Enables the Receive Equalizer within the corresponding channel For virtually all applications, we recommend that the user set this bit- OTE field to "1" (for all channels) and enable the Receive Equalizer. 76 XRT75R12 OCATION XM ESCRIPTION ...
Page 80
... YPE PRBS Generator and Receiver Enable - Channel_n: This READ/WRITE bit-field is used to enable or disable the PRBS Generator and Receiver within a given Channel of the XRT75R12. If the user enables the PRBS Generator and Receiver, then the following will happen. 1. The PRBS Generator (which resides within the Transmit Section of ...
Page 81
... This READ/WRITE bit-field, along with Bit 1 (STS-1/DS3_n) within this reg- ister, is used to configure a given channel into either the DS3 STS-1 Modes Configures Channel_n to operate in either the DS3 or STS-1 Modes, depending upon the state of Bit 1 (STS-1/DS3_n) within this same register. 1- Configures Channel_n to operate in the E3 Mode. 78 XRT75R12 OCATION XM ESCRIPTION ...
Page 82
... XRT75R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR T 40 ABLE HANNEL UMBER AME 1 DS3 R/W STS- SR/DR_n R ONTROL EGISTER HANNEL DDRESS (n = [0:11] & = 0-5 & 8- YPE STS-1/DS3 Mode Select - Channel_n: This READ/WRITE bit-field, along with Bit 2 (E3_n) is used to configure a given channel into either the DS3 STS-1 Modes. This bit-field is ignored if Bit 2 (E3_n) has been set to " ...
Page 83
... TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR REV. 1.0.4 T 41: XRT75R12 R ABLE EGISTER Reserved T 42 ABLE ITTER TTENUATOR UMBER AME Reserved 3 JA RESET Ch_n 2 JA1 Ch_n MAP J A SHOWING ITTER TTENUATOR ...
Page 84
... XRT75R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR T 42 ABLE ITTER TTENUATOR UMBER AME Path Ch_n 0 JA0 Ch_n T 43: XRT75R12 R ABLE EGISTER A DDRESS OCATION 0x0- APST IER0 ISR0 AS0 0 1- IER1 ISR1 ...
Page 85
... TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR REV. 1.0.4 T 45: XRT75R12 R ABLE EGISTER A DDRESS OCATION 0x0- APST IER0 ISR0 AS0 0 1- IER1 ISR1 AS1 X 0x2- IER2 ISR2 AS2 0x3- IER3 ISR3 AS3 0x4- IER4 ISR4 AS4 0x5- IER5 ...
Page 86
... XRT75R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR T 47: XRT75R12 R ABLE EGISTER A DDRESS OCATION 0x0- APST IER0 ISR0 AS0 0 1- IER1 ISR1 AS1 X 0x2- IER2 ISR2 AS2 0x3- IER3 ISR3 AS3 0x4- IER4 ISR4 AS4 0x5- IER5 ...
Page 87
... ARAMETER pattern pattern pattern pattern pattern pattern XRT75R12 UNITS COMMENTS V Note 1 V Note 1 mA Note 1 0 Note Industrial Temp Grade C 0 linear air flow 200ft/min C/W (See Note 3 below) 0 All conditions C/W level EIA/JEDEC ...
Page 88
... XRT75R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR T ABLE SYMBOL P STS1 Power Consumption CC_STS1 P STS1 Power Consumption with Jitter Attenuator Enabled CC_STS1JA V 2 Input Low Voltage Input High Voltage IH V Output Low Voltage OUT V Output High Voltage, I ...
Page 89
... MIN MAX MIN A 0.051 0.067 1.30 A1 0.020 0.028 0.50 A2 0.031 0.039 0.80 D 1.370 1.386 34.80 D1 1.250 BSC 31.75 BSC b 0.024 0.035 0.60 e 0.0500 BSC 1.27 BSC P 0.006 0.012 0.15 86 XRT75R12 PERATING EMPERATURE ANGE ° ° FEATURE/MARK ...
Page 90
... D EVISION ATE 1.0.0 05/10/05 Final Release Version of XRT75R12 datasheet. 1.0.1 April 2006 1.Added current and power consumption on Table 50, “DC Electrical Characteristics:,” on page 84. 2. Revised Receive Monitor Enable Bit functional description and Section 3. Updated Table 3, “The ALOS (Analog LOS) Declaration and Clearance Thresholds for a given setting of REQEN (DS3 and STS-1 Applications),” ...