sta381bws STMicroelectronics, sta381bws Datasheet - Page 57

• Manufacturer Part Number: sta381bws
• Description: Sound Terminal 2.1-channel High-efficiency Digital Audio System Sound Terminal 2.1-channel High-efficiency Digital Audio System
• Manufacturer: STMicroelectronics

STA381BWS
6.12
6.13
6.13.1
HPCFG register (addr 0x10)
Table 26.
Configuration register A (addr 0x11)
Master clock select
Table 27.
The STA381BWS supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,
176.4 kHz, and 192 kHz. Therefore the internal clock is:
●
●
●
The external clock frequency provided to the XTI pin or BICKI pin (depending on MCS
settings) must be a multiple of the input sample frequency (f
The relationship between the input clock (either XTI or BICKI) and the input sample rate is
determined by both the MCSx and the IR (input rate) register bits. The MCSx bits determine
the PLL factor generating the internal clock and the IR bit determines the oversampling ratio
used internally. In
clock source, while XTI is used in all the other cases.
Reserved
Bit
Bit
FDRB
0
0
1
2
D7
D7
32.768 MHz for 32 kHz
45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz
49.152 MHz for 48 kHz, 96 kHz, and 192 kHz
0
0
R/W
R/W
R/W
R/W
R/W
R/W
HPCFG register
Master clock select
Reserved
Reserved
D6
D6
0
1
Table 28
RST
RST
1
1
1
1
Reserved
Reserved
D5
D5
0
1
MCS 111 and 110 indicate that BICKI has to be used as the
Doc ID 018937 Rev 2
MUTE
MCS0
MCS1
MCS2
Name
Name
Reserved
IR1
D4
D4
0
0
Description
‘0’: HP/Line out is ON
‘1’: HP/LIne out is muted
Description
Selects the ratio between the input I
frequency and the input clock.
Reserved
IR0
D3
D3
0
0
Register description: New Map
Reserved
s
MCS2
).
D2
D2
0
1
Reserved
MCS1
D1
D1
0
1
2
S sample
MUTE
MCS0
D0
D0
1
1
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