sta381bws STMicroelectronics, sta381bws Datasheet - Page 152

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sta381bws

Manufacturer Part Number
sta381bws
Description
Sound Terminal 2.1-channel High-efficiency Digital Audio System Sound Terminal 2.1-channel High-efficiency Digital Audio System
Manufacturer
STMicroelectronics
Datasheet

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Register description: Sound Terminal compatibility
7.22.5
7.22.6
7.23
152/168
Power-down delay selector (PNDLSL[2:0]) bits (address 0x4C, bit D4,
D3, D2)
As per
million clock cycles puts the power bridge in tristate mode, independently from the fadeout
time. Using these registers it is possible to program this counter according to the following
table.
Table 171. PNDLSL bits configuration
Short-circuit check enable bit (address 0x4C, bit D0)
This bit, when enabled, will activate the short-circuit checks before any power bridge
activation (EAPD bit 0->1). See section
Bad PWM detection registers (address 0x4D, 0x4E, 0x4F)
PNDLSL[2]
BPTIM[7]
BPTH[5]
BP4B
D7
D7
D7
0
0
0
0
0
0
0
1
1
1
1
Section
BPTIM[6]
BPTH[4]
BP4A
7.22.2, the assertion of PWDN activates a counter that, by default, after 13
PNDLSL[1]
D6
D6
D6
0
0
1
0
0
1
1
0
0
1
1
BPTIM[5]
BPTH[3]
BP3B
D5
D5
D5
1
0
0
Doc ID 018937 Rev 2
PNDLSL[2]
0
1
0
1
0
1
0
1
BPTIM[4]
BPTH[2]
BP3A
D4
D4
D4
1
0
1
7.20
for more details.
BPTIM[3]
BPTH[1]
BP2B
Default time (13M PLL clock cycles)
D3
D3
D3
0
0
1
Default time divided by 128
Default time divided by 16
Default time divided by 32
Default time divided by 64
Default time divided by 2
Default time divided by 4
Default time divided by 8
BPTIM[2]
BPTH[0]
BP2A
Fade out time
D2
D2
D2
0
0
1
BPTIM[1]
reserved
BP1B
D1
D1
D1
1
0
1
STA381BWS
BPTIM[0]
reserved
BP1A
D0
D0
D0
0
0
0

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