sta381bws STMicroelectronics, sta381bws Datasheet - Page 120

• Manufacturer Part Number: sta381bws
• Description: Sound Terminal 2.1-channel High-efficiency Digital Audio System Sound Terminal 2.1-channel High-efficiency Digital Audio System
• Manufacturer: STMicroelectronics

Register description: Sound Terminal compatibility
7.6.2
7.6.3
7.6.4
7.6.5
7.6.6
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Invalid input detect mute enable
Table 125. Invalid input detect mute enable
Setting the IDE bit enables this function, which looks at the input I
mutes if the signals are perceived as invalid.
Binary output mode clock loss detection
Table 126. Binary output mode clock loss detection
Detects loss of input MCLK in binary mode and will output 50% duty cycle.
LRCK double trigger protection
Table 127. LRCK double trigger protection
Actively prevents double triggering of LRCLK.
Auto EAPD on clock loss
Table 128. Auto EAPD on clock loss
When active, issues a device power-down signal (EAPD) on clock loss detection.
IC power-down
Table 129. IC power-down
The PWDN register is used to place the IC in a low-power state. When PWDN is written
as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted
to power down the power stage, then the master clock to all internal hardware except the I
block is gated. This places the IC in a very low power consumption state.
Bit
Bit
Bit
Bit
Bit
2
3
4
5
7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RST
RST
RST
RST
RST
1
0
1
1
1
Name
LDTE
Name
ECLE
Name
Name
BCLE
PWDN
Name
IDE
Doc ID 018937 Rev 2
LRCLK double trigger protection enable
Binary output mode clock loss detection enable
Auto EAPD on clock loss
Setting of 1 enables the automatic invalid input detect mute
0: IC power-down low-power condition
1: IC normal operation
Description
Description
Description
Description
Description
2
S data and automatically
STA381BWS
2
C