lan91c100 Standard Microsystems Corp., lan91c100 Datasheet - Page 74

• Manufacturer Part Number: lan91c100
• Description: Feast ? Ast Ethernet Controller
• Manufacturer: Standard Microsystems Corp.

HIGH-END ISA MACHINES
On ISA machines, the LAN91C100 is accessed
as a 16 bit peripheral. No support for XT (8 bit
IOCHRDY
nIOCS16
ISA BUS
SIGNAL
D0-D15
A1-A15
nIOWR
RESET
nSBHE
nIORD
IRQn
AEN
A0
LAN91C100 SIGNAL
Table 4 - High-End ISA Machines Signal Connections
nLDEV buffered
INTR0-INTR3
D0-D15
A1-A15
RESET
ARDY
nBE0
nBE1
nWR
AEN
nRD
Address bus used for I/O space and register decoding
Qualifies valid I/O decoding - enabled access when low
I/O Read strobe - asynchronous read accesses. Address
is valid before leading edge
I/O Write strobe - asynchronous write access. Address is
valid before leading edge. Data is latched on trailing edge
This signal is negated on leading nRD, nWR if
necessary. It is then asserted on CLK rising edge after
the access condition is satisfied.
16 bit data bus. The bus byte(s) used to access the
device are a function of nBE0 and nBE1:
Not used = tri-state on reads, ignored on writes.
nLDEV is a totem pole output. Must be buffered using an
open collector driver. nLDEV is active on valid decodes
of A15-A4 and AEN=0.
nBE0
0
0
1
74
peripheral) is provided. The signal connections
are listed in the following table:
nBE1
0
1
0
NOTES
Not Used
D0-D7
Lower
Lower
Not Used
D8-D15
Upper
Upper