lan91c100 Standard Microsystems Corp., lan91c100 Datasheet - Page 37

• Manufacturer Part Number: lan91c100
• Description: Feast ? Ast Ethernet Controller
• Manufacturer: Standard Microsystems Corp.

101 5)
110 6)
111
Note 1: Bits N2,N1,N0 bits are ignored by the LAN91C100 but should be used for Command 0) to
Note 2: When using the RESET TX FIFOS command, the CPU is responsible for releasing the
Note 3: MMU commands releasing memory (commands 4 and 5) should only be issued if the
COMMAND SEQUENCING
A second allocate command (command 1)
should not be issued until the present one has
completed.
reading the FAILED bit of the allocation result
register or through the allocation interrupt.
A second release command (commands 4, 5)
should not be issued if the previous one is still
being processed. The BUSY bit indicates that a
release command is in progress. After issuing
RELEASE SPECIFIC PACKET - Frees all pages allocated to the packet specified in the
PACKET NUMBER REGISTER.
Typically used to remove transmitted frames, after reading their completion status. Can be
used following 3) to release receive packet memory in a more flexible way than 4).
ENQUEUE PACKET NUMBER INTO TX FIFO - This is the normal method of transmitting a
packet just loaded into RAM. The packet number to be enqueued is taken from the PACKET
NUMBER REGISTER.
7)
preserve software compatibility with the LAN91C92 and future devices. They should be zero
for all other commands.
memory associated with outstanding packets, or re-enqueuing them. Packet numbers in the
completion FIFO can be read via the FIFO ports register before issuing the command.
corresponding packet number has memory allocated to it.
Completion is determined by
RESET TX FIFOs - This command will reset both TX FIFOs--theTX FIFO holding
the packet numbers awaiting transmission and the TX Completion FIFO.
command provides a mechanism for canceling packet transmissions, and reordering
or bypassing the transmit queue. The RESET TX FIFOs command should only be
used when the transmitter is disabled. Unlike the RESET MMU command, the
RESET TX FIFOs does not release any memory.
Should not be used for frames pending transmission.
37
command 5, the contents of the PNR should not
be changed until BUSY goes low. After issuing
command 4, command 3 should not be issued
until BUSY goes low.
BUSY BIT
command register address. When set indicates
that
command.
completed last release command. BUSY and
FAILED bits are set upon the trailing edge of
command.
MMU
When clear, MMU has already
Readable at bit 0 of the MMU
is
still
processing
a
release
This