lan91c100 Standard Microsystems Corp., lan91c100 Datasheet - Page 42

• Manufacturer Part Number: lan91c100
• Description: Feast ? Ast Ethernet Controller
• Manufacturer: Standard Microsystems Corp.

I/O SPACE - BANK2
This register can be read and written as a word
or as two individual bytes.
The Interrupt Mask Register bits enable the
appropriate bits when high and disable them
when low. An enabled bit being set will cause a
hardware interrupt.
ERCV INT
whenever a receive packet is being received,
and the number of bytes received into memory
OFFSET
OFFSET
OFFSET
X
X
C
C
D
ERCV INT
ERCV INT
ERCV INT
Early receive interrupt.
0
0
INTERRUPT STATUS REGISTER
INTERRUPT MASK REGISTER
INTERRUPT ACKNOWLEDGE
EPH INT
EPH INT
0
0
REGISTER
NAME
NAME
NAME
RX_OVRN
RX_OVRN
RX_OVRN
INT
INT
INT
0
0
Set
42
ALLOC
ALLOC
exceeds the value programmed as ERCV
THRESHOLD (Bank 3, Offset Ch). ERCV INT
stays set until acknowledged by writing the
INTERRUPT ACKNOWLEDGE REGISTER with
the ERCV INT bit set.
EPH INT
Handler section indicates one out of various
possible special conditions.
exception type of interrupt sources, whose
service time is not critical to the execution speed
INT
INT
0
0
EMPTY
WRITE ONLY
EMPTY
READ/WRITE
EMPTY
READ ONLY
Set when the Ethernet Protocol
INT
INT
INT
TX
TX
TX
1
0
TYPE
TYPE
TYPE
TX INT
TX INT
TX INT
0
0
This bit merges
SYMBOL
SYMBOL
SYMBOL
MSK
ACK
IST
RCV INT
RCV INT
0
0