lan91c100 Standard Microsystems Corp., lan91c100 Datasheet - Page 53

• Manufacturer Part Number: lan91c100
• Description: Feast ? Ast Ethernet Controller
• Manufacturer: Standard Microsystems Corp.

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ISSUE ALLOCATE MEMORY FOR TX - N
BYTES
bytes of RAM.
WAIT FOR SUCCESSFUL COMPLETION
CODE - Poll until the ALLOC INT bit is set or
enable its mask bit and wait for the interrupt.
The TX packet number is now at the Allocation
Result Register.
LOAD TRANSMIT DATA - Copy the TX packet
number into the Packet Number Register.
Write the Pointer Register, then use a block
move operation from the upper layer transmit
queue into the Data Register.
ISSUE "ENQUEUE PACKET NUMBER TO TX
FIFO" - This command writes the number
present in the Packet Number Register into the
TX FIFO. The transmission is now enqueued.
transmit interrupt is generated.
SERVICE INTERRUPT - Read Interrupt Status
Register. If it is a transmit interrupt, read the
TX Done Packet Number from the Fifo Ports
Register. Write the packet number into the
Packet Number Register. The corresponding
status word is now readable from memory. If
status word shows successful transmission,
issue RELEASE packet number command to
free up the memory used by this packet.
Remove packet number from completion FIFO
by writing TX INT Acknowledge Register.
No further CPU intervention is needed until a
- the MMU attempts to allocate N
S/W DRIVER
TYPICAL FLOW OF EVENTS FOR TRANSMIT
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The enqueued packet will be transferred to the
MAC block as a function of TXENA (n TCR) bit
and of the deferral process state.
Upon transmit completion the first word in
memory is written with the status word. The
packet number is moved from the TX FIFO
into the TX completion FIFO.
generated by the TX completion FIFO being
not empty.
MAC SIDE
Interrupt is