lan91c100 Standard Microsystems Corp., lan91c100 Datasheet - Page 39

• Manufacturer Part Number: lan91c100
• Description: Feast ? Ast Ethernet Controller
• Manufacturer: Standard Microsystems Corp.

I/O SPACE - BANK2
This register provides access to the read ports of the Receive FIFO and the Transmit completion
FIFO. The packet numbers to be processed by the interrupt service routines are read from this
register.
REMPTY No receive packets queued in the RX
FIFO. For polling purposes, uses the RCV_INT
bit in the Interrupt Status Register.
TOP OF RX FIFO PACKET NUMBER Packet
number presently at the output of the RX FIFO.
Only valid if REMPTY is clear. The packet is
removed from the RX FIFO using MMU
Commands 3) or 4).
TEMPTY
queue. For polling purposes, uses the TX_INT
bit in the Interrupt Status Register.
BYTE
BYTE
HIGH
LOW
OFFSET
4
No transmit packets in completion
REMPTY
TEMPTY
1
1
0
0
FIFO PORTS REGISTER
NAME
0
0
39
0
0
TX DONE PACKET NUMBER Packet number
presently at the output of the TX Completion
FIFO.
packet is removed when a TX INT acknowledge
is issued.
Note: For software compatibility with future
versions, the value read from each FIFO register
is intended to be written into the PNR as is,
without masking higher bits (provided TEMPTY
and REMPTY = 0 respectively).
TX DONE PACKET NUMBER
RX FIFO PACKET NUMBER
0
0
Only valid if TEMPTY is clear.
READ ONLY
TYPE
0
0
0
0
SYMBOL
FIFO
0
0
The