mpc604e Freescale Semiconductor, Inc, mpc604e Datasheet - Page 5

• Manufacturer Part Number: mpc604e
• Description: Powerpc 604e-tm Risc Microprocessor Technical Summary
• Manufacturer: Freescale Semiconductor, Inc

PowerPC 604e RISC Microprocessor Technical Summary
1.1.2 Overview of the PowerPC 604e Microprocessor Features
Major features of the 604e are as follows:
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— Support for additional processor/bus clock ratios (5:2 and 4:1). Configuration of the processor/
— To support the changes in the clocking configuration, different precharge timings for the ABB,
— No-DRTRY mode. In addition to the normal and fast L2 modes implemented on the 604, a no-
Full hardware support for little-endian accesses. Little-endian accesses take alignment exceptions
for only the same set of causes as big-endian accesses. Accesses that cross a word boundary require
two accesses with the lower-addressed word accessed first.
Additional enhancements to the performance monitor.
High-performance, superscalar microprocessor
— As many as four instructions can be issued per clock
— As many as seven instructions can start executing per clock (including three integer
— Single-clock-cycle execution for most instructions
Seven independent execution units and two register files
— BPU featuring dynamic branch prediction
— Condition register logical unit
— Two single-cycle IUs (SCIUs) and one multiple-cycle IU (MCIU)
bus clock ratios is displayed through a new 604e-specific register, HID1.
DBB, ARTRY, and SHD signals are implemented internally by the processor. The precharge
timings for ARTRY and SHD can be disabled by setting HID0[7].
DRTRY mode is implemented on the 604e that improves performance on read operations for
systems that do not use the DRTRY signal. No-DRTRY mode makes read data available to the
processor one bus clock cycle sooner than in normal mode . In no-DRTRY mode, the DRTRY
signal is no longer sampled as part of a qualified bus grant.
instructions)
– Two-entry reservation station
– Out-of-order execution through two branches
– Shares dispatch bus with CRU
– 64-entry fully-associative branch target address cache (BTAC). In the 604e, the BTAC can
– 512-entry branch history table (BHT) with two bits per entry for four levels of prediction—
– Two-entry reservation station
– Shares dispatch bus with BPU
– Instructions that execute in the SCIU take one cycle to execute; most instructions that
– Each SCIU has a two-entry reservation station to minimize stalls
– The MCIU has a single-entry reservation station and provides early exit (three cycles)
– Thirty-two GPRs for integer operands
be disabled and invalidated.
not-taken, strongly not-taken, taken, strongly taken
execute in the MCIU take multiple cycles to execute.
for 16- x 32-bit and overflow operations.
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