mpc604e Freescale Semiconductor, Inc, mpc604e Datasheet
mpc604e
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mpc604e Summary of contents
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... The PowerPC 604e microprocessors are available from IBM as PPC604e and from Motorola as MPC604e. The PowerPC name, the PowerPC logotype, PowerPC 604, and PowerPC 604e, are trademarks of International Business Machines Corporation, used by Motorola under license from International Business Machines Corporation ...
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Part 1 PowerPC 604e Microprocessor Overview This section describes the features of the 604e, provides a block diagram showing the major functional units, and describes briefly how those units interact. The 604e is an implementation of the PowerPC family of ...
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Time Base Counter/Decrementer Clock JTAG/COP Multiplier Interface Reservation Reservation Station (2 Entry) Station (2 Entry) Multiple- Single-Cycle Cycle Integer Integer Units Unit / / + * * + 32 Bit 32 Bit COMPLETION UNIT 16-Entry Reorder Buffer Store Queue 32-BIT ...
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New Features of the PowerPC 604e Processor Features of the 604e that are not implemented in the 604 are as follows: • Additional special-purpose registers — HID1 provides four read-only PLL_CFG bits for indicating the processor/bus clock ratio. — ...
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Support for additional processor/bus clock ratios (5:2 and 4:1). Configuration of the processor/ bus clock ratios is displayed through a new 604e-specific register, HID1. — To support the changes in the clocking configuration, different precharge timings for the ABB, ...
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Three-stage floating-point unit (FPU) – Fully IEEE 754-1985-compliant FPU for both single- and double-precision operations – Supports non-IEEE mode for time-critical operations – Fully pipelined, single-pass double-precision design – Hardware support for denormalized numbers – Two-entry reservation station to ...
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Caches can be locked — Parity checking performed on both caches — Data cache coherency (MESI) maintained in hardware — Secondary data cache support provided — Instruction cache coherency maintained in hardware — Data cache line-fill buffer forwarding. In ...
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Performance monitor can be used to help in debugging system designs and improving software efficiency, especially in multiprocessor systems. • In-system testability and debugging features through JTAG boundary-scan capability 1.2 PowerPC 604e Microprocessor Hardware Implementation This section provides an ...
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Instruction Flow Several units on the 604e ensure the proper flow of instructions and operands and guarantee the correct update of the architectural machine state. These units include the following: • Fetch unit—Using the next sequential address or the ...
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The 512-entry BHT provides two bits per entry, indicating four levels of dynamic prediction—strongly not- taken, not-taken, taken, and strongly taken. The history of a branch’s direction is maintained in these two bits. Each time a branch is taken the ...
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The instruction is retired from the reorder buffer when it has finished execution and all instructions ahead of it have been completed. The instruction’s result is written into the appropriate register file and is removed from the rename buffers at ...
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Floating-Point Unit (FPU) The FPU, shown in Figure 1 and Figure single-pass, double-precision execution unit; that is, most single- and double-precision operations require only a single pass, with a latency of three cycles. As the decode/dispatch ...
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Address translations are enabled by setting bits in the MSR—MSR[IR] enables instruction address translations and MSR[DR] enables data address translations. The 604e’s MMUs support Petabytes ( virtual memory and 4 Gigabytes ( ...
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To ensure cache coherency, the 604e data cache supports the four-state MESI (modified/exclusive/shared/ invalid) protocol. The data ...
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System Interface/Bus Interface Unit (BIU) The 604e provides a versatile bus interface that allows a wide variety of system design options. The interface includes a 72-bit data bus (64 bits of data and 8 bits of parity), a 36-bit ...
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Address tenures for address-only transactions can exceed this limit. Typically, memory accesses are weakly-ordered. Sequences of operations, including load/store string/ multiple instructions, do not necessarily complete in ...
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Data arbitration signals—The 604e uses these signals to arbitrate for data bus mastership. • Data transfer signals—These signals, which consist of the data bus, data parity, and data parity error signals, are used to transfer the data and to ...
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BUS REQUEST ADDRESS BUS GRANT ARBITRATION ADDRESS BUS BUSY ADDRESS TRANSFER START START EXTENDED TRANSFER START ADDRESS ADDRESS ADDRESS PARITY TRANSFER ADDRESS PARITY ERROR TRANSFER TYPE TRANSFER CODE TRANSFER SIZE TRANSFER BURST CACHE INHIBIT TRANSFER ATTRIBUTE WRITE THROUGH GLOBAL CACHE ...
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The 604e supports the following processor-to-bus clock frequency ratios—1:1, 3:2, 2:1, 5:2, 3:1, and 4:1, although not all ratios are available for all frequencies. Configuration of the processor/bus clock ratios is displayed through a 604e-specific register, HID1. Part 2 PowerPC ...
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The PowerPC architecture consists of the following layers, and adherence to the PowerPC architecture can be measured in terms of which of the following levels of the architecture is implemented: • PowerPC user instruction set architecture (UISA)—Defines the base user-level ...
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USER MODEL UISA General-Purpose Registers GPR0 GPR1 GPR31 Floating-Point Registers FPR0 FPR1 FPR31 Condition Register CR Floating-Point Status and Control Register FPSCR XER XER SPR 1 Link Register LR SPR 8 Count Register CTR SPR 9 USER MODEL VEA Time ...
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PowerPC processors have two levels of privilege—supervisor mode of operation (typically used by the operating environment) and one that corresponds to the user mode of operation (used by application software). As shown in Figure 6, the programming model incorporates 32 ...
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Segment Registers (SRs) For memory management, 32-bit PowerPC implementations use sixteen 32-bit segment registers (SRs). 2.1.1.7 Special-Purpose Registers (SPRs) The PowerPC operating environment architecture defines numerous special-purpose registers that serve a variety of functions, such as providing controls, indicating ...
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In the 604e. the time base frequency is 1/4th of the bus clock frequency (as is the decrementer frequency). Counting is enabled by the Time Base Enable (TBE) signal. • Block address translation (BAT) ...
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Logical instructions — Integer rotate and shift instructions • Floating-point instructions—These include floating-point computational instructions, as well as instructions that affect the FPSCR. Floating-point instructions include the following: — Floating-point arithmetic instructions — Floating-point multiply/add instructions — Floating-point rounding ...
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The TLB Synchronize (tlbsync) instruction ensures that all tlbie instructions previously executed by the processor that issued the tlbsync instruction have completed. • Processor control instructions—These instructions are used for synchronizing memory accesses and managing caches, TLBs, and segment ...
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Effective address computations for both data and instruction accesses use 32-bit unsigned binary arithmetic. A carry from bit 0 is ignored in the 604e. 2.1.3 Exception Model The following subsections describe the PowerPC exception model and the 604e implementation, respectively. ...
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Asynchronous—The OEA portion of the PowerPC architecture defines two types of asynchronous exceptions: — Asynchronous, maskable—The PowerPC architecture defines the external interrupt and decrementer interrupt which are maskable and asynchronous exceptions. In the 604e, and in many PowerPC processors, ...
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The 604e’s exceptions, and conditions that cause them, are listed in Table 2. Exception Vector Offset Type (hex) Reserved 00000 System reset 00100 Machine 00200 check DSI 00300 ISI 00400 PowerPC 604e RISC Microprocessor Technical Summary Table 2. Exceptions and ...
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Table 2. Exceptions and Conditions (Continued) Exception Vector Offset Type (hex) External 00500 An external interrupt occurs when the external interrupt signal, INT, is asserted. interrupt This signal is expected to remain asserted until the exception handler begins execution. Once ...
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Table 2. Exceptions and Conditions (Continued) Exception Vector Offset Type (hex) Reserved 00E10–00EFF Performance 00F00 monitoring interrupt Reserved 01000–012FF Instruction 01300 address breakpoint System 01400 management interrupt Reserved 01500-02FFF Reserved 01000–02FFF 2.1.4 Instruction Timing As shown in Figure 7, the ...
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SCIU1 SCIU2 The common pipeline stages are as follows: • Instruction fetch (IF)—During the IF stage, the fetch unit loads the decode queue (DEQ) with instructions from the instruction cache and determines from ...
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The execution unit reports any internal exceptions to the completion stage and continues execution, regardless of the exception. Under some circumstances, results can be written directly to the target registers, bypassing the rename buffers. • Complete (C)—The completion stage ensures ...
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Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors. There are no express or implied copyright or patent licenses granted hereunder by Motorola or IBM to design, modify the design of, or ...