mpc604e Freescale Semiconductor, Inc, mpc604e Datasheet - Page 27

• Manufacturer Part Number: mpc604e
• Description: Powerpc 604e-tm Risc Microprocessor Technical Summary
• Manufacturer: Freescale Semiconductor, Inc

PowerPC 604e RISC Microprocessor Technical Summary
Effective address computations for both data and instruction accesses use 32-bit unsigned binary arithmetic.
A carry from bit 0 is ignored in the 604e.
2.1.3 Exception Model
The following subsections describe the PowerPC exception model and the 604e implementation,
respectively.
The PowerPC exception mechanism allows the processor to change to supervisor state as a result of external
signals, errors, or unusual conditions arising in the execution of instructions. When exceptions occur,
information about the state of the processor is saved to various registers and the processor begins execution
at an address (exception vector) predetermined for each exception and the processor changes to supervisor
mode.
Although multiple exception conditions can map to a single exception vector, a more specific condition may
be determined by examining a register associated with the exception—for example, the DSISR and the
FPSCR. Additionally, specific exception conditions can be explicitly enabled or disabled by software.
The PowerPC architecture requires that exceptions be handled in program order; therefore, although a
particular PowerPC processor may recognize exception conditions out of order, exceptions are handled
strictly in order. When an instruction-caused exception is recognized, any unexecuted instructions that
appear earlier in the instruction stream, including any that have not yet entered the execute state, are
required to complete before the exception is taken. Any exceptions caused by those instructions must be
handled first. Likewise, exceptions that are asynchronous and precise are recognized when they occur
(unless they are masked) and the reorder buffer is drained. The address of the next sequential instruction is
saved in SRR0 so execution can resume in the correct context when the exception handler returns control
to the interrupted process.
Unless a catastrophic condition causes a system reset or machine check exception, only one exception is
handled at a time. If, for example, a single instruction encounters multiple exception conditions, those
conditions are encountered sequentially. After the exception handler handles an exception, the instruction
execution continues until the next exception condition is encountered. This method of recognizing and
handling exception conditions sequentially guarantees that exceptions are recoverable.
Exception handlers should save the information stored in SRR0 and SRR1 early to prevent the program state
from being lost due to a system reset or machine check exception or to an instruction-caused exception in
the exception handler.
The PowerPC architecture supports four types of exceptions:
•
•
Synchronous, precise—These are caused by instructions. All instruction-caused exceptions are
handled precisely; that is, the machine state at the time the exception occurs is known and can be
completely restored.
Synchronous, imprecise—The PowerPC architecture defines two imprecise floating-point
exception modes, recoverable and nonrecoverable. The 604e implements only the imprecise,
nonrecoverable mode. The imprecise, recoverable mode is treated as the precise mode in the 604e.
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