mpc604e Freescale Semiconductor, Inc, mpc604e Datasheet - Page 29

• Manufacturer Part Number: mpc604e
• Description: Powerpc 604e-tm Risc Microprocessor Technical Summary
• Manufacturer: Freescale Semiconductor, Inc

PowerPC 604e RISC Microprocessor Technical Summary
The 604e’s exceptions, and conditions that cause them, are listed in Table 2.
Reserved
System reset
Machine
check
DSI
ISI
Exception
Type
00000
00100
00200
00300
00400
Vector Offset
(hex)
—
A system reset is caused by the assertion of either the soft or hard reset signal.
A machine check exception is signaled by the assertion of a qualified TEA
indication on the 604e bus, or the machine check input (MCP) signal. If the
MSR[ME] is cleared, the processor enters the checkstop state when one of
these signals is asserted. Note that MSR[ME] is cleared when an exception is
taken. The machine check exception is also caused by parity errors on the
address or data bus or in the instruction or data caches.
The assertion of the TEA signal is determined by load and store operations
initiated by the processor; however, it is expected that the TEA signal would be
used by a memory controller to indicate that a memory parity error or an
uncorrectable memory ECC error has occurred.
Note that the machine check exception is imprecise with respect to the
instruction that originated the bus operation.
The cause of a DSI exception can be determined by the bit settings in the
DSISR, listed as follows:
An ISI exception is caused when an instruction fetch cannot be performed for
any of the following reasons:
Table 2. Exceptions and Conditions
• The effective address cannot be translated. That is, a page fault occurred for
• The fetch access is to a direct-store segment.
• The fetch access violates memory protection. If the key bits (Ks and Kp) in
• An attempt is made to fetch an instruction from a segment configured as no-
• An attempt is made to fetch an instruction from a block or page configured
0 Set if a load or store instruction results in a direct-store exception;
1 Set if the translation of an attempted access is not found in the primary
4 Set if a memory access is not permitted by the page or DBAT protection
5 If SR[T] = 1, set by an eciwx, ecowx, lwarx, or stwcx. instruction;
6 Set for a store operation and cleared for a load operation.
9 Set if an EA matches the address in the DABR while in one of the three
10 Set if the segment table search fails to find a translation for the effective
11 Set if eciwx or ecowx is used and EAR[E] is cleared.
this part of the translation, so an ISI exception must be taken to retrieve the
translation from a storage device such as a hard disk drive.
the segment register and the PP bits in the PTE or IBAT are set to prohibit
read access, instructions cannot be fetched from this location.
execute; that is, SR[N] = 1.
as guarded, that is the G bit is set and translation is enabled, MSR[IR] = 1.
otherwise cleared.
table entry group (PTEG), or in the rehashed secondary PTEG, or in the
range of a BAT register; otherwise cleared.
mechanism; otherwise cleared.
otherwise cleared. Set by an eciwx or ecowx instruction if the access is to
an address that is marked as write-through.
compare modes.
address; otherwise cleared.
Causing Conditions
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