mpc604e Freescale Semiconductor, Inc, mpc604e Datasheet - Page 11

• Manufacturer Part Number: mpc604e
• Description: Powerpc 604e-tm Risc Microprocessor Technical Summary
• Manufacturer: Freescale Semiconductor, Inc

The instruction is retired from the reorder buffer when it has finished execution and all instructions ahead
of it have been completed. The instruction’s result is written into the appropriate register file and is removed
from the rename buffers at or after completion. At completion, the 604e also updates any other resource
affected by this instruction. Several instructions can complete simultaneously. Most exception conditions
are recognized at completion time.
1.2.7 Rename Buffers
To avoid contention for a given register location, the 604e provides rename registers for storing instruction
results before the completion unit commits them to the architected register. Twelve rename registers are
provided for the GPRs, eight for the FPRs, and eight for the condition register. GPRs are described in
Section 2.1.1.1, “General-Purpose Registers (GPRs),” FPRs are described in Section 2.1.1.2, “Floating-
Point Registers (FPRs),” and the condition register is described in Section 2.1.1.3, “Condition Register
(CR).”
When the dispatch unit dispatches an instruction to its execution unit, it allocates a rename register for the
results of that instruction. The dispatch unit also provides a tag to the execution unit identifying the result
that should be used as the operand. When the proper result is returned to the rename buffer it is latched into
the reservation station. When all operands are available in the reservation station, the execution can begin.
The completion unit does not transfer instruction results from the rename registers to the registers until any
branch conditions preceding it in the completion queue are resolved and the instruction itself is retired from
the completion queue without exceptions. If a branch is found to have been incorrectly predicted, all
instructions following the branch are flushed from the completion queue and any results of those
instructions are flushed from the rename registers.
1.2.8 Execution Units
The following sections describe the 604e’s arithmetic execution units—the two single-cycle integer units
(SCIUs), the multiple cycle integer unit (MCIU), and the FPU. When the reservation station sees the proper
result being written back, it will grab it directly from one of the result buses. Once all operands are in the
reservation station for an instruction, it is eligible to be executed. Reservation stations temporarily store
dispatched instructions that cannot be executed until all of the source operands are valid.
1.2.8.1 Integer Units (IUs)
The two SCIUs and one MCIU execute all integer instructions. These are shown in Figure 1 and Figure 2.
Each IU has a dedicated result bus that connects to rename buffers and to all reservation stations. Each SCIU
has a two-entry reservation station and the MCIU has a single-entry reservation station to reduce stalls. A
reservation station can receive instructions from the decode/dispatch unit and operands from the GPRs, the
rename buffers, or the result buses.
Each SCIU consists of three single-cycle subunits—a fast adder/comparator, a subunit for logical
operations, and a subunit for performing rotates, shifts, and count-leading-zero operations. These subunits
handle all one-cycle arithmetic instructions; only one subunit can execute an instruction at a time.
The MCIU consists of a 32-bit integer multiplier/divider. The multiplier supports early exit on 16- x 32-bit
operations, and is responsible for executing the Move from Special-Purpose Register ( mfspr) and Move to
Special-Purpose Register ( mtspr) instructions, which are used to read and write special-purpose registers.
Note that the load and store instructions that update their address base register (specified by the r A operand)
pass the update results on the MCIU’s result bus. Otherwise, the MCIU’s result bus is dedicated to MCIU
operations.
PowerPC 604e RISC Microprocessor Technical Summary
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