mpc604e Freescale Semiconductor, Inc, mpc604e Datasheet - Page 14

• Manufacturer Part Number: mpc604e
• Description: Powerpc 604e-tm Risc Microprocessor Technical Summary
• Manufacturer: Freescale Semiconductor, Inc

cache block flush ( dcbf ) instruction, and cache block clean operations resulting from the data cache block
store ( dcbst ) instruction.
To ensure cache coherency, the 604e data cache supports the four-state MESI (modified/exclusive/shared/
invalid) protocol. The data cache tags are dual-ported, so the process of snooping does not affect other
transactions on the system interface. If a snoop hit occurs, the LSU is blocked internally for one cycle to
allow the eight-word block of data to be copied to the writeback buffer.
Like the instruction cache, the data cache can be invalidated all at once or on a per cache block basis. The
data cache can be disabled and invalidated by setting the HID0[17] and HID0[21] bits, respectively. The
data cache can be locked by setting HID0[19].
Each cache line contains eight contiguous words from memory that are loaded from an eight-word boundary
(that is, bits A27–A31 of the physical addresses are zero); thus, a cache line never crosses a page boundary.
Accesses that cross a page boundary can incur a performance penalty.
To ensure coherency among caches in a multiprocessor (or multiple caching-device) implementation, the
604e implements the MESI protocol on a per cache-block basis. MESI stands for modified/exclusive/
shared/invalid. These four states indicate the state of the cache block as follows:
Figure 3 describes the cache unit organization on the 604e.
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Block 0
Block 1
Block 2
Block 3
•
•
•
•
Modified (M)—The cache block is modified with respect to system memory; that is, data for this
address is valid only in the cache and not in system memory.
Exclusive (E)—This cache block holds valid data that is identical to the data at this address in
system memory. No other cache has this data.
Shared (S)—This cache block holds valid data that is identical to this address in system memory
and at least one other caching device.
Invalid (I)—This cache block does not hold valid data.
256 Sets
Address Tag 0
Address Tag 1
Address Tag 2
Address Tag 3
Figure 3. Cache Unit Organization
State
State
State
State
PowerPC 604e RISC Microprocessor Technical Summary
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