mpc5554mzp80r2 Freescale Semiconductor, Inc, mpc5554mzp80r2 Datasheet - Page 56

• Manufacturer Part Number: mpc5554mzp80r2
• Description: Mpc5554 High Performance Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Revision History for the MPC5554 Data Sheet
56
Revision
Rev. 2.0
Table 12
Table 13
Table 14
Table 15
(T
Table 16
Table 27
• Added (T
• Old footnote 2: ‘Nominal crystal and external reference values are worst-case not more than
• Deleted old footnote 18 from row 21, from the MAX column that reads:
• Added (T
• Moved footnote 1 from the table title to directly after the ‘Typical’ in the column 5 header.
• Footnote 2: Changed from: ‘Initial factory condition: ≤ 100 program/erase cycles, 25
• Added footnote 1 to the end of the table title, The footnote reads: ‘Illegal combinations exist.
• Moved footnote 2:’ For maximum flash performance, set to 0b11’ to the ‘DPFEN’ column
• Deleted the x-refs in the ‘DPFEN’ column for the rows.
• Created a x-ref for footnote 2 and inserted in the ‘IPFEN’ column header.
• Deleted the x-refs in the ‘IPFEN’ column for the rows.
• Moved footnote 3:’ For maximum flash performance, set to 0b110’ to the ‘PFLIM’ column
• Deleted the x-refs in the ‘PFLIM’ column for the rows.
• Moved footnote 4:’ For maximum flash performance, set to 0b1’ to the ‘BFEN’ column header.
• Deleted the x-refs in the ‘BFEN’ column for the rows.
• Deleted first header row that reads ‘CLOAD = 25 pF on all outputs. Pad drive strength set to
• Deleted from footnote 1: ‘F
A
1%. The device operates correctly if the frequency remains within ± 5% of the specification
limit. This tolerance range allows for a slight frequency drift of the crystals over time. The
designer must thoroughly understand the drift margin of the source clock.‘ was moved
to the end of 1st row in column 2: ‘PLL reference frequency range.’ moving the footnote
location changed it to footnote 1. Deleted old footnote 2 from all Min and Max columns.
The ICO frequency can be higher than the maximum allowable system frequency. For this
case, set the CMPLL synthesizer control register reduced frequency divider
(FMPLL_SYNCR[RFD]) to divide-by-two (RFD = 0b001). Therefore, for a 40 MHz maximum
device (system frequency), program the FMPLL to generate 80 MHz at the ICO output and
then divide-by-two the RFD to provide the 40 MHz system clock.’
supply voltage, 80 MHz minimum system frequency.‘ To: ‘Initial factory condition: ≤ 100
program/erase cycles, 25
frequency of 80 MHz.’
Use entries from the same row in this table.’
header.
header.
maximum.’
V.’ and changed ‘CL = 50 pF’ to ‘CL = 25 pF.’
= T
L
– T
FMPLL Electrical Characteristics:
eQADC Conversion Specifications: Added (T
Flash Program and Erase Specifications:
Flash EEPROM Module Life Specifications: Replaced (Full Temperature Range) with
Flash BIU Settings vs. Frequency of Operation:
eQADC SSI Timing Characteristics:
A
A
H
) in the table title.
= T
= T
L
L
– T
– T
H
H
Table 28. MPC5554 Revision History (continued)
MPC5554 Microcontroller Data Sheet, Rev. 2.0
) to the second line of the table title.
) to the table title.
o
SYS
C, using a typical supply voltage measured at a minimum system
= 132 MHz, V
Substantive Change(s)
DD
= 1.35–1.65 V, V
A
= T
L
– T
H
) to the table title.
DD33
and V
DDSYN
o
Freescale Semiconductor
= 3.0–3.6
C, typical
9/20/07
Date