mpc5554mzp80r2 Freescale Semiconductor, Inc, mpc5554mzp80r2 Datasheet - Page 12
mpc5554mzp80r2
Manufacturer Part Number
mpc5554mzp80r2
Description
Mpc5554 High Performance Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MPC5554MZP80R2.pdf
(58 pages)
Electrical Characteristics
To avoid this condition, minimize the ramp time of the V
required to enable the external circuitry connected to the device outputs.
3.7.1
When powering up the device, V
more than the V
bypass clock mode because the internal versions of PLLCFG[0:1] and RSTCFG are not powered and
therefore cannot read the default state when POR negates. V
pin (V
applies during power up only. V
3.7.2
The 1.5 V V
power supply rises above 2.0 V. This ensures that digital logic in the PLL for the 1.5 V power supply does
not begin to operate below the specified operation range lower limit of 1.35 V. Because the internal 1.5 V
POR is disabled, the internal 3.3 V POR or the RESET power POR must hold the device in reset. Since
they can negate as low as 2.0 V, V
POR negate.
3.7.3
The only requirement for the power-down sequence when V
less than its operating range, V
V
reset by the ORed POR only and can cause the 1.5 V supply to decrease below its specification, is reset
properly.
12
DD
power is allowed to increase to its operating range. This ensures that the digital 1.5 V logic, which is
DDEH6
Input Value of Pins During POR Dependent on V
Power-Up Sequence (V
Power-Down Sequence (V
DD
), but cannot lag both by more than the V
power supply must rise to 1.35 V before the 3.3 V V
DD33
V
DD
2.0 V
must reach 1.35 V before V
lag specification listed in
Figure 2. Power-Up Sequence (V
DDSYN
DD33
MPC5554 Microcontroller Data Sheet, Rev. 2.0
DD33
DD
1.35 V
has no lead or lag requirements when powering down.
must be within specification before the 3.3 V POR and the RESET
must not lag the latest V
or the RESET power must decrease to less than 2.0 V before the
DDSYN
RC33
Table
RC33
and the RESET power reach 2.0 V
Grounded)
DD33
6, spec 8. This avoids accidentally selecting the
Grounded)
DD
lag specification. This V
DD33
RC33
supply to a time period less than the time
RC33
DDSYN
V
Grounded)
is grounded is that if V
can lag V
DDSYN
DDSYN
or RESET power pin (V
and RESET Power
power supply and the RESET
DDSYN
V
DD
DD33
DD33
or the RESET power
Freescale Semiconductor
lag specification
DD
decreases to
DDEH6
) by