mpc5554mzp80r2 Freescale Semiconductor, Inc, mpc5554mzp80r2 Datasheet - Page 39

no-image

mpc5554mzp80r2

Manufacturer Part Number
mpc5554mzp80r2
Description
Mpc5554 High Performance Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1
2
3
4
5
6
Freescale Semiconductor
Spec
10
11
12
All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad type M or MH. DSPI signals using pad types of
S or SH have an additional delay based on the slew rate. DSPI timing is specified at: V
and CL = 50 pF with SRC = 0b11.
The minimum SCK cycle time restricts the baud rate selection for the given system clock rate.
These numbers are calculated based on two MPC55xx devices communicating over a DSPI link.
The actual minimum SCK cycle time is limited by pad performance.
The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK].
The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC].
This number is calculated using the SMPL_PT field in DSPI_MCR set to 0b10.
9
Data setup time for inputs
Data hold time for inputs
Data valid (after SCK edge)
Data hold time for outputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
Characteristic
MPC5554 Microcontroller Data Sheet, Rev. 2.0
6
6
Table 26. DSPI Timing
Symbol
t
t
SUO
t
SUI
t
HO
HI
Min
5.5
20
–4
20
–4
21
–4
–5
–5
2
7
8
80 MHz
1
Max
25
18
(continued)
5
5
Min
5.5
20
20
–4
14
–4
–5
–5
2
3
7
4
112 MHz
DDEH
Max
25
14
5
5
= 3.0–5.5 V;T
Electrical Characteristics
Min
5.5
20
20
–4
12
–4
–5
–5
2
6
7
3
132 MHz
A
= T
Max
L
25
13
5
5
to T
H
;
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
39

Related parts for mpc5554mzp80r2