mpc5554mzp80r2 Freescale Semiconductor, Inc, mpc5554mzp80r2 Datasheet
mpc5554mzp80r2
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mpc5554mzp80r2 Summary of contents
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... The embedded architecture has enhancements that improve the performance in embedded applications. The core also has additional instructions, including digital signal processing (DSP) instructions, beyond the original Power PC instruction set. © Freescale Semiconductor, Inc., 2007. All rights reserved. Document Number: MPC5554 Rev. 2.0, 10/2007 Contents 1 Overview ...
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Overview The MPC5500 family of parts contains many new features coupled with high performance CMOS technology to provide significant performance improvement over the MPC565. The MPC5554 of the MPC5500 family has two levels of memory hierarchy. The fastest accesses are ...
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Ordering Information Operating frequency (MHz) Package Identifier Temperature Range ZP = 416PBGA SnPb M = –40° 125° 416PBGA Pb-free A = –55° 125° C Note: Not all options are available on all ...
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Electrical Characteristics 3 Electrical Characteristics This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MCU. 3.1 Maximum Ratings Spec Characteristic 2 1 1.5 V core supply voltage 2 Flash program/erase voltage 4 ...
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Table 2. Absolute Maximum Ratings Spec Characteristic 28 Maximum solder temperature Lead free (PbFree) Leaded (SnPb Moisture sensitivity level 1 Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and ...
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Electrical Characteristics 5 Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. 6 Thermal characterization ...
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At a known board temperature, the junction temperature is estimated using the following equation θ where junction temperature ( board temperature at the package perimeter ( B R ...
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Electrical Characteristics so that the thermocouple junction rests on the package. Place a small amount of epoxy on the thermocouple junction and approximately wire extending from the junction. Place the thermocouple wire flat against the package case ...
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ESD (Electromagnetic Static Discharge) Characteristics Characteristic ESD for human body model (HBM) HBM circuit description ESD for field induced charge model (FDCM) Number of pulses per pin: Positive pulses (HBM) Negative pulses (HBM) Interval of pulses 1 All ESD ...
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Electrical Characteristics Table 6. VRC/POR Electrical Specifications (continued) Spec Characteristic 8 Voltage differential during power up such that: V can lag DD33 DDSYN reach the V and V POR33 POR5 9 Absolute value of slew rate on ...
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Furthermore, when all of the PORs negate, the system clock starts to toggle, adding another large increase of the current consumed by V RC33 consumed can drop V low enough to assert the 1.5 V POR again. Oscillations are possible ...
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Electrical Characteristics To avoid this condition, minimize the ramp time of the V required to enable the external circuitry connected to the device outputs. 3.7.1 Input Value of Pins During POR Dependent on V When powering up the device, V ...
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DC Electrical Specifications Spec Characteristic 1 Core supply voltage (average DC RMS voltage) 2 Input/output supply voltage (fast input/output) 3 Input/output supply voltage (slow and medium input/output) 4 3.3 V input/output buffer voltage 5 Voltage regulator control input voltage ...
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Electrical Characteristics Table 9. DC Electrical Specifications (continued) Spec Characteristic 27a Operating Current 1.5 V Supplies @ 132 MHz: V (including V max current) @1.65 V typical use DD DDF V (including V max current) @1.4 V typical use DD ...
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Table 9. DC Electrical Specifications (continued) Spec Characteristic 12 30 Operating current V supplies: DDE V DDEH1 V DDE2 V DDE3 V DDEH4 V DDE5 V DDEH6 V DDE7 V DDEH8 V DDEH9 13 31 Fast I/O weak pullup current ...
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Electrical Characteristics 2 V can drop to 3.0 V during read operations standby operation is not required, connect V 4 Applies to CLKOUT, external bus pins, and Nexus pins. 5 Maximum average RMS DC current. 6 Figure ...
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Figure 3 shows an approximate interpolation of the I values at different voltages and temperatures. Refer to the I ο vertical lines shown 2000 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 ...
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Electrical Characteristics 3.8.1 I/O Pad Current Specifications The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The power consumption is the sum of all output pin currents for a segment. The ...
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I/O Pad V DD33 The power consumption of the V power consumption is the sum of all input and output pin V pin V current can be calculated from DD33 (pad_fc) pins. The input pin V DD33 frequency, and ...
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Electrical Characteristics 3.9 Oscillator and FMPLL Electrical Characteristics (V DDSYN Spec Characteristic PLL reference frequency range: Crystal reference 1 External reference Dual controller (1:1 mode System frequency 3 System clock period 4 Loss of reference frequency 5 Self-clocked ...
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Table 12. FMPLL Electrical Specifications (continued) (V DDSYN Spec Characteristic 13, 14 CLKOUT period jitter, measured at f maximum: 19 Peak-to-peak jitter (clock edge to clock edge) Long term jitter (averaged over interval) Frequency modulation range limit ...
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Electrical Characteristics 3.10 eQADC Electrical Characteristics Table 13. eQADC Conversion Specifications ( Spec Characteristic 1 ADC clock (ADCLK) frequency Conversion cycles 2 Differential Single ended 2 3 Stop mode recovery time 3 4 Resolution 5 INL: 6 MHz ADC clock ...
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H7Fa Flash Memory Electrical Characteristics Spec Table 14. Flash Program and Erase Specifications (T Spec Flash Program Characteristic 3 Doubleword (64 bits) program time 4 4 Page program time block pre-program and erase time 9 48 ...
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Electrical Characteristics Table 16 shows the FLASH_BIU settings versus frequency of operation. Refer to the device reference manual for definitions of these bit fields. Table 16. FLASH_BIU Settings vs. Frequency of Operation Maximum Frequency (MHz and including ...
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Table 17. Pad AC Specifications (V Spec Pad 3 Fast 4 Pullup/down (3.6 V max) 5 Pullup/down (5.5 V max) 1 These are worst-case values that are estimated from simulation (not tested). The values in the table are simulated at: ...
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Electrical Characteristics 3 The output delay, and the rise and fall, are calculated to 20% or 80% of the respective signal. 4 The output delay is shown in Figure system clock to the output delay. 5 This parameter is guaranteed ...
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RESET RSTOUT 3 PLLCFG BOOTCFG RSTCFG WKPCFG Figure 5. Reset and Configuration Pin Timing 3.13.2 IEEE 1149.1 Interface Timing Table 20. JTAG Pin AC Electrical Characteristics Spec Characteristic 1 TCK cycle time 2 TCK clock pulse width (measured at V ...
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Electrical Characteristics TCK 3 TCK TMS, TDI TDO 28 1 Figure 6. JTAG Test Clock Input Timing Figure 7. JTAG Test Access Port Timing MPC5554 Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor ...
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TCK JCOMP Freescale Semiconductor 9 Figure 8. JTAG JCOMP Timing MPC5554 Microcontroller Data Sheet, Rev. 2.0 Electrical Characteristics 10 29 ...
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Electrical Characteristics TCK 11 Output signals 12 Output signals Input signals 30 14 Figure 9. JTAG Boundary Scan Timing MPC5554 Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor ...
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Nexus Timing Spec Characteristic 1 MCKO cycle time 2 MCKO duty cycle 3 MCKO low to MDO data valid 4 MCKO low to MSEO data valid 5 MCKO low to EVTO data valid 6 EVTI pulse width 7 EVTO ...
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Electrical Characteristics TCK TMS, TDI TDO 3.13.4 External Bus Interface (EBI) Timing Table 22 lists the timing information for the external bus: Characteristic and Spec Description 1 CLKOUT period 2 CLKOUT duty cycle 3 CLKOUT rise time 4 CLKOUT fall ...
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Characteristic and Spec Description CLKOUT positive edge to output signal invalid or Hi-Z (hold time) External bus interface ADDR[8:31 CS[0:3] DATA[0:31] BDIP OE RD_WR TA TEA TS TSIZ[0:1] WE/BE[0:3] CLKOUT positive edge to output ...
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Electrical Characteristics Characteristic and Spec Description Input signal valid to CLKOUT positive edge (setup time) External bus interface ADDR[8:31 DATA[0:31] BDIP OE RD_WR TA TEA TS TSIZ[0:1] WE/BE[0:3] CLKOUT positive edge to input signal ...
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Vol_f CLKOUT CLKOUT 5 Output ÷ DDE bus 5 Output ÷ DDE signal Output signal Freescale Semiconductor Voh_f 3 4 Figure 12. CLKOUT Timing 6 6 Figure 13. Synchronous Output Timing MPC5554 Microcontroller Data Sheet, Rev. ...
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Electrical Characteristics CLKOUT Input bus Input ÷ 2 signal V DDE 3.13.5 External Interrupt Timing (IRQ Signals) Spec Characteristic 1 IRQ pulse-width low 2 IRQ pulse-width high 2 3 IRQ edge-to-edge time 1 IRQ timing specified at 1.35–1.65 ...
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IRQ 1 3.13.6 eTPU Timing Spec Characteristic 1 eTPU input channel pulse width 2 eTPU output channel pulse width 1 eTPU timing specified at 3.0–5.5 V; and T DDEH 2 This specification does not include the rise and ...
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Electrical Characteristics 3.13.7 eMIOS Timing Spec 1 eMIOS input pulse width 2 eMIOS output pulse width 1 eMIOS timing specified at 3.0–5.5 V; and T DDEH 2 This specification does not include the rise and fall times. When ...
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Spec Characteristic Data setup time for inputs Master (MTFE = 0) 9 Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) Data hold time for inputs Master (MTFE = 0) 10 Slave Master (MTFE ...
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Electrical Characteristics PCSx SCK output (CPOL=0) SCK output (CPOL=1) SIN SOUT Figure 18. DSPI Classic SPI Timing—Master, CPHA = 0 PCSx SCK output (CPOL=0) SCK output (CPOL=1) SIN SOUT Figure 19. DSPI Classic SPI Timing—Master, CPHA = ...
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SS SCK input (CPOL=0) SCK input (CPOL=1) SOUT SIN Figure 20. DSPI Classic SPI Timing—Slave, CPHA = 0 SS SCK input (CPOL=0) SCK input (CPOL=1) SOUT SIN Figure 21. DSPI Classic SPI Timing—Slave, CPHA = 1 Freescale Semiconductor 2 4 ...
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Electrical Characteristics PCSx SCK output (CPOL=0) SCK output (CPOL=1) SIN SOUT Figure 22. DSPI Modified Transfer Format Timing—Master, CPHA = 0 PCSx SCK output (CPOL=0) SCK output (CPOL=1) SIN SOUT Figure 23. DSPI Modified Transfer Format Timing—Master, CPHA = 1 ...
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SS SCK input (CPOL=0) SCK input (CPOL=1) SOUT SIN Figure 24. DSPI Modified Transfer Format Timing—Slave, CPHA = 0 SS SCK input (CPOL=0) SCK input (CPOL=1) SOUT SIN Figure 25. DSPI Modified Transfer Format Timing—Slave, CPHA = 1 PCSS PCSx ...
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Electrical Characteristics 3.13.9 eQADC SSI Timing Table 27. EQADC SSI Timing Characteristics Spec Rating ÷ 2 FCK period ( FCK FCK 3 Clock (FCK) high time 4 Clock (FCK) low time 5 SDS lead / lag time ...
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Mechanicals 4.1 MPC5554 416 PBGA Pinouts Figure 28, Figure 29, and Figure VSS VSTBY AN37 AN11 VDDA1 AN16 AN1 AN5 AN0 AN4 B VDD VSS AN36 AN39 AN19 AN20 ...
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Mechanicals VSS VSTBY AN37 B VDD VSS AN36 C VDD33 VDD VSS ETPUA ETPUA D VDD 30 31 ETPUA ETPUA VDDEH ETPUA ETPUA ETPUA ETPUA ETPUA ETPUA G ...
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ETRIG ETPUB VSSA0 AN15 1 18 ETRIG ETPUB VSSA0 AN14 0 21 ETPUB ETPUB VDDA0 AN13 19 22 VDDEH ETPUB ETPUB AN12 VDDE7 VDDE7 VDDE7 VDDE7 VSS VSS VSS VDDE7 VSS VSS VSS ...
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Mechanicals 4.2 MPC5554 416-Pin Package Dimensions The package drawings of the MPC5554 416 pin TEPBGA package are shown in 48 Figure 31. MPC5554 416 TEPBGA Package MPC5554 Microcontroller Data Sheet, Rev. 2.0 Figure 31. Freescale Semiconductor ...
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Figure 32. MPC5554 416 TEPBGA Package (continued) Freescale Semiconductor MPC5554 Microcontroller Data Sheet, Rev. 2.0 Mechanicals 49 ...
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Revision History for the MPC5554 Data Sheet Revision History for the 5 Table 28 shows the revision history of the MPC5554 Data Sheet: . Table 28. MPC5554 Data Sheet Revision History Revision Rev. 1.3 Published Rev 1.3 of MPC5554 Data ...
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Table 28 shows a continuation of the MPC5554 Revision History: Revision Rev. 2.0 Table 2 Absolute Maximum Ratings: • Increased the maximum operating frequency values the Max column for the 80 MHz and 112 MHz. • ...
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Revision History for the MPC5554 Data Sheet Revision Rev. 2.0 Table 7 Power Sequence Pin Status for the Fast Pad: Changed preceding paragraph From: Although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive current spikes, ...
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Revision Rev. 2.0 Table 14 Flash Program and Erase Specifications: Inserted new values for the H7Fa Flash pre-program and erase times and used the previous values for Typical and Initial Max values. • Typical Values — 16 KB: from 325 ...
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Revision History for the MPC5554 Data Sheet Revision Rev. 2.0 Figure 1 MPC5500 Family Part Numbers: • Added footnote 1 to read: All devices are PPC5554, rather than MPC5554, until the product qualifications are complete. Not all configurations are available ...
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Revision Rev. 2.0 Section 3.7.1, “Input Value of Pins During POR Dependent on Added the following text directly before this section and after Pads During the Power-on Sequence: ‘The values in Table 7 output pins during power up. Before exiting ...
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Revision History for the MPC5554 Data Sheet Revision Rev. 2.0 Table 12 FMPLL Electrical Characteristics: • Added ( – • Old footnote 2: ‘Nominal crystal and external reference values are worst-case not more than 1%. ...
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Revision Rev. 2.0 Table 17 Pad AC Specifications 5 V: • Footnote 1, deleted ‘f • Footnote 2, changed from ‘tested’ to ‘not tested.’ • Footnote 3, changed from ‘Out delay. . .’ to ‘The output delay. . .’, • ...
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... Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. All rights reserved. ...