mc68hc912bc32 Freescale Semiconductor, Inc, mc68hc912bc32 Datasheet - Page 269

• Manufacturer Part Number: mc68hc912bc32
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

16.12.7 msCAN12 Transmitter Flag Register
The abort acknowledge flags are read only. The transmitter buffer empty flags are read and clear only. A flag
can be cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect on the flag setting.
Each transmitter buffer empty flag has an associated interrupt enable bit in the CTCR register. A hard or soft
reset resets the register.
ABTAK2–ABTAK0 — Abort Acknowledge Flag
TXE2–TXE0 —Transmitter Buffer Empty Flag
Freescale Semiconductor
This flag acknowledges that a message has been aborted due to a pending abort request from the
CPU. After a particular message buffer has been flagged empty, this flag can be used by the
application software to identify whether the message has been aborted successfully or has been sent
in the meantime. The ABTAKx flag is cleared implicitly whenever the corresponding TXE flag is
cleared.
This flag indicates that the associated transmit message buffer is empty, thus not scheduled for
transmission. The CPU must handshake (clear) the flag after a message has been set up in the
transmit buffer and is due for transmission. The msCAN12 sets the flag after the message has been
sent successfully. The flag is also set by the msCAN12 when the transmission request was aborted
successfully due to a pending abort request. See
If not masked, a transmit interrupt is pending while this flag is set.
Clearing a TXEx flag also clears the corresponding ABTAKx flag. When a TXEx flag is set, the
corresponding ABTRQx bit is cleared. See
0 = The message has not been aborted; it has been sent.
1 = The message has been aborted.
0 = The associated message buffer is full (loaded with a message due for transmission).
1 = The associated message buffer is empty (not scheduled).
Address: $0106
To ensure data integrity, no registers of the transmit buffers should be
written to while the associated TXE flag is cleared.The CTFLG register is
held in the reset state if the SFTRES bit CMCR0 is set.
Reset:
Read:
Write:
Figure 16-22. msCAN12 Transmitter Flag Register (CTFLG)
Bit 7
0
0
= Unimplemented
ABTAK2
6
0
M68HC12B Family Data Sheet, Rev. 9.1
ABTAK1
5
0
16.12.8 msCAN12 Transmitter Control
NOTE
ABTAK0
4
0
16.12.8 msCAN12 Transmitter Control
3
0
0
Programmer’s Model of Control Registers
TXE2
2
1
TXE1
1
1
Register.
TXE0
Bit 0
1
Register.
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