mc68hc912bc32 Freescale Semiconductor, Inc, mc68hc912bc32 Datasheet - Page 255

• Manufacturer Part Number: mc68hc912bc32
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

The clock source bit (CLKSRC) in the msCAN12 module control register (CMCR1) (see
msCAN12 Bus Timing Register
oscillator (EXTALi) or to a clock twice as fast as the system clock (ECLK).
The clock source has to be chosen so that the tight oscillator tolerance requirements (up to 0.4 percent)
of the CAN protocol are met. Additionally, for high CAN bus rates (1 Mbps), a 50 percent duty cycle of the
clock is required.
For microcontrollers without the CGM module, CGMCANCLK is driven from the crystal oscillator
(EXTALi).
A programmable prescaler is used to generate out of msCANCLK the time quanta (Tq) clock. A time
quantum is the atomic unit of time handled by the msCAN12.
A bit time is subdivided into three segments
The synchronization jump width can be programmed in a range of 1 to 4 time quanta by setting the SJW
parameter. These parameters can be set by programming the bus timing registers (CBTR0 and CBTR1).
See
1. For further explanation of the underlying concepts, refer to ISO/DIS 11519-1, Section 10.3.
Freescale Semiconductor
•
•
•
16.12.3 msCAN12 Bus Timing Register 0
SYNC_SEG — This segment has a fixed length of one time quantum. Signal edges are expected
to happen within this section.
Time segment 1 — This segment includes the PROP_SEG and the PHASE_SEG1 of the CAN
standard. It can be programmed by setting the parameter TSEG1 to consist of 4 to 16 time quanta.
Time segment 2 — This segment represents the PHASE_SEG2 of the CAN standard. It can be
programmed by setting the TSEG2 parameter to be 2 to 8 time quanta.
It is the user’s responsibility to make sure that the bit time settings are in
compliance with the CAN standard.
CAN-conforming segment settings and the related parameter values.
SYSCLK
EXTALi
0) defines whether the msCAN12 is connected to the output of the crystal
BitRate
CLKSRC
M68HC12B Family Data Sheet, Rev. 9.1
Figure 16-7. Clocking Scheme
CGM
=
f
Tq
(1)
---------------------------------------------------------------------------- -
number
=
:
CGMCANCLK
-------------------------------------- -
Presc
f
and
NOTE
CGMCANCLK
Table 16-3
Þ
16.12.4 msCAN12 Bus Timing Register
of
Þ
f
Þ
value
Tq
TimeQuanta
MSCAN12
PRESCALER
(1...64)
gives an overview on the
CLKSRC
TIME QUANTA
CLOCK
16.12.3
Clock System
1.
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