mc68hc912bc32 Freescale Semiconductor, Inc, mc68hc912bc32 Datasheet - Page 136

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mc68hc912bc32

Manufacturer Part Number
mc68hc912bc32
Description
M68hc12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Pulse-Width Modulator (PWM)
11.2.12 PWM Control Register
Read: Anytime
Write: Anytime
PSWAI — PWM Halts While in Wait Mode Bit
CENTR — Center-Aligned Output Mode Bit
RDPP — Reduced Drive of Port P Bit
PUPP — Pullup Port P Enable Bit
PSBCK — PWM Stops While in Background Mode Bit
136
To avoid irregularities in the PWM output mode, write the CENTR bit only when PWM channels are
disabled.
0 = Continue PWM main clock generator while in wait mode.
1 = Halt PWM main clock generator when the part is in wait mode.
0 = PWM channels operate in left-aligned output mode.
1 = PWM channels operate in center-aligned output mode.
0 = Full drive for all port P output pins
1 = Reduced drive for all port P output pins
0 = Disable port P pullups
1 = Enable pullups for all port P input pins.
0 = Allows PWM to continue while in background mode
1 = Disable PWM input clock while in background mode.
Address: $0054
Reset:
Read:
Write:
Bit 7
0
0
Figure 11-24. PWM Control Register (PWCTL)
= Unimplemented
6
0
0
M68HC12B Family Data Sheet, Rev. 9.1
5
0
0
PSWAI
4
0
CENTR
3
0
RDPP
2
0
PUPP
1
0
Freescale Semiconductor
PSBCK
Bit 0
0

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