mc68hc912bc32 Freescale Semiconductor, Inc, mc68hc912bc32 Datasheet - Page 114

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mc68hc912bc32

Manufacturer Part Number
mc68hc912bc32
Description
M68hc12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Clock Generation Module (CGM)
10.3 Register Map
10.4 Clock Selection and Generation
The CGM generates the P clock, the E clock, and four T clocks. The P clock and E clock are used by all
device modules except the CPU. The T clocks are used by the CPU.
Figure 10-3
There are two types of P clocks and E clocks while in wait mode:
Figure 10-4
114
$0014
$0015
$0016
$0017
$00E0
Addr.
Global type (G), which is driven by the slow clock divider in wait mode and drives all on-chip
peripherals except the BDLC and the TIMER
Global type (GBT), which remains at the oscillator divide-by-2 rate in wait mode and drives the
BDLC and the TIMER
Real-Time Interrupt Flag Register
COP Control Register (COPCTL)
Slow Mode Divider Register
Real-Time Interrupt Control
shows clock timing relationships while in normal run modes.
shows clock timing relationships while in wait mode.
Register Name
Arm/Reset COP Timer
Register (COPRST)
Register (RTICTL)
See page 118.
See page 119.
See page 119.
See page 120.
See page 117.
(RTIFLG)
(SLOW)
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
M68HC12B Family Data Sheet, Rev. 9.1
Figure 10-2. CGM Register Map
RTIE
RTIF
CME
Bit 7
Bit 7
0
0
0
0
0
0
= Unimplemented
RSWAI
FCME
Bit 6
6
0
0
0
0
0
0
0
RSBCK
FCM
Bit 5
5
0
0
0
0
0
0
0
FCOP
Bit 4
4
0
0
0
0
0
0
0
0
RTBYP
DISR
Bit 3
3
0
0
0
0
0
0
0
SLDV2
RTR2
CR2
Bit 2
2
0
0
0
0
0
0
Freescale Semiconductor
SLDV1
RTR1
CR1
Bit 1
1
0
0
0
0
0
0
SLDV0
RTR0
Bit 0
CR0
Bit 0
0
0
0
1
0
0

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