mc68hc912bc32 Freescale Semiconductor, Inc, mc68hc912bc32 Datasheet - Page 245

• Manufacturer Part Number: mc68hc912bc32
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

16.3.2 Receive Structures
The received messages are stored in a 2-stage first-in/first-out (FIFO) input. The two message buffers are
mapped into a single memory area (see
exclusively associated to the msCAN12, the foreground receive buffer (RxFG) is addressable by the
CPU12. This scheme simplifies the handler software since only one address area is applicable for the
receive process.
Both buffers have 13 bytes for storing the CAN control bits, the identifier (standard or extended), and the
data contents. For details, see
The receiver full flag (RXF) in the msCAN12 receiver flag register (CRFLG) signals the status of the
foreground receive buffer. When the buffer contains a correctly received message with matching
identifier, this flag is set. See
On reception, each message is checked to see if it passes the filter (for details see
Acceptance
RxFG
to read the received message from RxFG and then reset the RXF flag to acknowledge the interrupt and
Freescale Semiconductor
(1)
, sets the RXF flag, and emits a receive interrupt to the CPU
Filter) and in parallel is written into RxBG. The msCAN12 copies the content of RxBG into
Figure 16-2. User Model for Message Buffer Organization
msCAN12
16.12.5 msCAN12 Receiver Flag
16.11 Programmer’s Model of Message
M68HC12B Family Data Sheet, Rev. 9.1
Figure
RxBG
Tx0
RxFG
Tx1
Tx2
16-2). While the background receive buffer (RxBG) is
PRIO
PRIO
PRIO
RXF
TXE
TXE
TXE
Register.
CPU BUS
(2)
. The user’s receive handler has
Storage.
16.4 Identifier
Message Storage
245