mc68hc908ap8a Freescale Semiconductor, Inc, mc68hc908ap8a Datasheet - Page 302

• Manufacturer Part Number: mc68hc908ap8a
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Electrical Specifications
302
Operating frequency
Bus free time
Repeated start hold time.
Repeated start setup time.
Stop setup time
Hold time
Setup time
Clock low time-out
Clock low
Clock high
Slave clock low extend time
Master clock low extend time
Fall time
Rise time
1. Devices participating in a transfer will timeout when any clock low exceeds the value of T
2. T
3. T
4. T
5. Rise and fall time is defined as follows: T
that have detected a timeout condition must reset the communication no later than T
value specified must be adhered to by both a master and a slave as it incorporates the cumulative limit for both a master
(10 ms) and a slave (25 ms).
Software should turn-off the MMIIC module to release the SDA and SCL lines.
to the stop. If a slave device exceeds this time, it is expected to release both its clock and data lines and reset itself.
defined from start-to-ack, ack-to-ack, or ack-to-stop.
HIGH MAX
LOW.SEXT
LOW.MEXT
Characteristic
provides a simple guaranteed method for devices to detect the idle conditions.
is the cumulative time a slave device is allowed to extend the clock cycles in one message from the initial start
is the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as
Table 22-9. MMIIC Interface Input/Output Signal Timing
t
t
LOW.MEXT
LOW.SEXT
Symbol
t
t
t
t
t
t
TIMEOUT
SU.STO
HD.STA
HD.DAT
SU.DAT
SU.STA
MC68HC908AP A-Family Data Sheet, Rev. 3
t
f
t
t
HIGH
SMB
LOW
BUF
t
t
R
F
R
= (V
ILMAX
Min
300
250
4.7
4.7
4.0
4.7
4.0
10
4.0
25
—
—
—
—
– 0.15) to (V
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1000
IHMIN
Max
100
300
35
—
—
—
—
—
—
—
—
25
10
+ 0.15), T
Unit
kHz
ms
ms
ms
µs
µs
µs
µs
ns
ns
µs
µs
ns
ns
F
MMIIC operating frequency
Bus free time between STOP and
START condition
Hold time after (repeated) START
condition. After this period, the first
clock is generated.
Repeated START condition setup time.
Stop condition setup time.
Data hold time.
Data setup time.
Clock low time-out.
Clock low period
Clock high period.
Cumulative clock low extend time (slave
device)
Cumulative clock low extend time
(master device)
Clock/Data Fall Time
Clock/Data Rise Time
= 0.9×V
TIMEOUT
(3)
TIMEOUT
DD
max of 35ms. The maximum
to (V
Comments
Freescale Semiconductor
(4)
min. of 25ms. Devices
ILMAX
(2)
(1)
(5)
(5)
– 0.15).