mc68hc908ap8a Freescale Semiconductor, Inc, mc68hc908ap8a Datasheet - Page 286

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mc68hc908ap8a

Manufacturer Part Number
mc68hc908ap8a
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Low-Voltage Inhibit (LVI)
an LVI reset occurs, the MCU remains in reset until V
V
LVIOUT flag in the LVI status register (LVISR).
An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices.
20.3.1 Low V
The low V
below the trip voltage, V
CONFIG1 register.
20.3.2 Low V
The low V
falls below the trip voltage, V
in CONFIG1 register.
20.3.3 Polled LVI Operation
In applications that can operate at V
the LVIOUT bit. In the CONFIG1 register, the LVIPWRD bit must be at logic 0 to enable the LVI module,
and the LVIRSTD bit must be at logic 1 to disable LVI resets.
286
TRIPR2
, which causes the MCU to exit reset. The output of the comparator controls the state of the
DD
REG
V
DETECTOR
DETECTOR
detector circuit monitors the V
LOW V
V
LOW V
REG
detector circuit monitors the V
DD
DD
REG
REG
Detector
DD
Detector
TRIPF1
V
V
V
V
FROM CONFIG1
FROM CONFIG1
DD
DD
REG
REG
TRIPF2
> V
≤ V
LVIPWRD
LVIREGD
> V
≤ V
. The V
Figure 20-2. LVI Module Block Diagram
TRIPR1
TRIPF1
TRIPR2
TRIPF2
MC68HC908AP A-Family Data Sheet, Rev. 3
. The V
DD
= 1
= 0
= 1
= 0
DD
levels below the V
LVI circuit can be disabled by the setting the LVIPWRD bit in
REG
DD
REG
LVI circuit can be disabled by the setting the LVIREGD bit
voltage and forces a LVI reset when the V
voltage and forces a LVI reset when the V
STOP INSTRUCTION
STOP INSTRUCTION
DD
TRIPF1
rises above V
TO LVISR
FROM CONFIG1
LVIOUT
level, software can monitor V
LVIRSTD
FROM CONFIG1
FROM CONFIG1
TRIPR1
LVISTOP
LVISTOP
and V
LVI RESET
Freescale Semiconductor
REG
rises above
DD
DD
voltage falls
REG
by polling
voltage

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