mc68hc908ap8a Freescale Semiconductor, Inc, mc68hc908ap8a Datasheet - Page 110

• Manufacturer Part Number: mc68hc908ap8a
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

System Integration Module (SIM)
Figure 7-16
7.6.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a
module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the clock generator module output (CGMOUT) in stop mode, stopping the CPU and
peripherals. Stop recovery time is selectable using the SSREC bit in the configuration register 1
(CONFIG1). If SSREC is set, stop recovery is reduced from the normal delay of 4096 ICLK cycles down
to 32. This is ideal for applications using canned oscillators that do not require long start-up times from
stop mode.
110
and
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
Figure 7-17
ICLK
RST
R/W
IDB
IAB
IDB
IAB
NOTE: Previous data can be operand data or the WAIT opcode, depending on the
IAB
IDB
$A6
Figure 7-16. Wait Recovery from Interrupt or Break
last instruction.
WAIT ADDR
$A6
Figure 7-17. Wait Recovery from Internal Reset
$6E0B
$A6
show the timing for WAIT recovery.
PREVIOUS DATA
$6E0B
Figure 7-15. Wait Mode Entry Timing
$A6
MC68HC908AP A-Family Data Sheet, Rev. 3
$A6
WAIT ADDR + 1
$A6
CYCLES
32
$6E0C
NEXT OPCODE
$01
NOTE
CYCLES
$00FF
32
$0B
SAME
$00FE
$6E
RST VCT H RST VCT L
SAME
$00FD
SAME
$00FC
SAME
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