pnx1500 NXP Semiconductors, pnx1500 Datasheet - Page 744

• Manufacturer Part Number: pnx1500
• Description: Pnx15xx Series Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
PNX15XX_SER_3
Product data sheet
6.3 Disabling the LAN100
6.4 Little/big Endian
6.5 Interrupts
6.6 Errors and Aborts
To enter coma mode, software should first enter sleep mode. The system’s
power-management controller can then disable the MMIO clock. To exit coma mode,
software should re-enable the MMIO clock before following the wake-up step from
Section
In implementations that do require Ethernet functionality, the external PHY can be
omitted, and the I/O pins from the PHY, including the clock inputs, can be tied to 0 or
1. In this case, software should switch the LAN100 to sleep mode by setting the
PowerDown bit in the PowerDown register.
The LAN100 memory interfaces take care of the conversion to the endian mode of
the PNX15xx Series system buses. When packing multiple Ethernet bytes into a word
in order to optimize bus traffic, the LAN100 orders the bytes as required by the
system bus. Internally, all components of the LAN100 use bytes as the native width
for transmission and reception of data. Therefore, the LAN100 itself is endian
insensitive.
The LAN100 has a single interrupt request output directed to the CPU.
After taking the interrupt, the CPU’s interrupt service routine must read the IntStatus
register to locate the origin of the interrupt. Software interrupt conditions can be set
by writing to the IntSet register; interrupt conditions can be cleared by writing to the
IntClear register.
The transmit and Receive Datapaths can only set interrupt status, they cannot clear
status. The SoftInt interrupt cannot be set by hardware and can be used by software
for test purposes.
For more information on the source of an interrupt refer to
Section
Several conditions cause the LAN100 to generate errors:
•
•
An illegal MMIO access can cause an MMIO error response as defined in
Section
propagated back to the CPU across the system bus.
If the PowerDown bit is set, any access to MMIO registers will result in an error
response except for access to the PowerDown register.
Packet reception can cause errors, including AlignmentError, RangeError,
LengthError, SymbolError, CRCError, NoDescriptor, and Overrun. These errors
are reported in the receive status word and in the interrupt status register. For
more information refer to
6.2.1.
5.5.7.
5.1. These errors are handled by the MMIO adapter, which may be
Rev. 3 — 17 March 2006
Chapter 23: LAN100 — Ethernet Media Access Controller
Section 4.1
and
Section
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
5.5.
PNX15xx Series
Section 5.4.8
and
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