pnx1500 NXP Semiconductors, pnx1500 Datasheet - Page 244

• Manufacturer Part Number: pnx1500
• Description: Pnx15xx Series Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
Table 8: Registers Description
PNX15XX_SER_3
Product data sheet
Bit
20:18
17
16
15
14:12
11
10
9:7
6:2
1
0
Offset 0x04 0014
31:17
16
15
14
13
12
11
Symbol
base18_siz
en_base18
base14_prefetchable
Reserved
base14_siz
en_base14
base10_prefetchable
base10_siz
Reserved
en_config_manag
en_pci_arb
Reserved
dis_swapper2targ
dis_swapper2intreg
dis_swapper2dtlinit
regs_wr_post_en
xio_wr_post_en
pci2_wr_post_en
PCI Control
Acces
s
R/W1
R/W1
R/W1
R
R/W1
R/W1
R/W1
R/W1
R/W1
R/W1
R
R/W
R/W
R/W
R/W
R/W
R/W
Value
011
1
0
0
000
1
1
100
1
0
0
0
0
0
0
0
0
Rev. 3 — 17 March 2006
Description
The size of aperture located by PCI cfg base18 is:
011 = 16 MB
100 = 32 MB
101 = 64 MB
110 = 128 MB
This aperture is used as the XIO aperture in the PNX15xx Series.
Note: If expanding to 128 MB, the default setting of base18 address
will overlap with the default base14 address. To avoid an address
conflict, the base18 address or the base14 address should be
relocated before setting the base18_siz.
Enable 3rd aperture, PCI base address 18. The PNX15xx Series
will always use this aperture.
PCI Base address 14 is a non-prefetchable memory aperture.
The size of aperture located by PCI cfg base 14 is 000 = 2 MB.
This aperture is used as the MMIO aperture in the PNX15xx Series.
Enable 2nd aperture, PCI base address 14. The PNX15xx Series
will always use this aperture.
PCI Base address 10 is a prefetchable memory aperture.
The size of aperture located by PCI cfg base 10 is:
011 = 16 MB
100 = 32 MB
101 = 64 MB
110 = 128 MB
This aperture is used as the DRAM aperture in the PNX15xx
Series.
Enable configuration management.
Enable internal PCI system arbitration.
0 = Enable byte swapping in big endian mode from DCS to PCI
path.
1 = Disable byte swapping in big endian mode from DCS to PCI
path.
0 = Enable byte swapping in big endian mode from PCI to PCI mmio
registers.
1 = Disable byte swapping in big endian mode from PCI to PCI
mmio registers.
0 = Enable byte swapping in big endian mode from PCI to DCS.
1 = Disable byte swapping in big endian mode from PCI to DCS.
Enable write posting to internal PCI registers.
Enable write posting to XIO address range.
Enable write posting to pci_base2 address range.
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Chapter 7: PCI-XIO Module
PNX15xx Series
7-25