pnx1500 NXP Semiconductors, pnx1500 Datasheet - Page 162

• Manufacturer Part Number: pnx1500
• Description: Pnx15xx Series Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
Table 6: DDS and PLL Clock Assignment
Table 7: External Clocks
PNX15XX_SER_3
Product data sheet
Source
PLL0
PLL1
PLL2
DDS0/PLL0
DDS1/PLL1
DDS2
DDS3
DDS4
DDS5
DDS6
DDS7
DDS8
Signal Name
xtal_clk
clk_pci
clk_pci_i
Destinations
clk_tm
clk_fgpo
clk_mem
clk_tm
clk_fgpo
clk_fgpo
ao_osclk
ai_osclk
clk_spdo
clk_gpio_q6_12
clk_vip
clk_gpio_q4
Frequency
27 MHz
33.23 MHz
up to 33.33 MHz
2.2.3 The DDS Clocks
2.2.4 DDS and PLL Assignment Summary
2.2.5 External Clocks
The DDS clocks are recommended for clocks that need to track dynamically another
frequency by very small steps. The following equations characterize the PNX15xx
Series DDS blocks:
registers
The
Series system.
Table 7
external clock is any in-coming clock that feeds a PNX15xx Series module or any
internal PNX15xx Series clock that can drive a PNX15xx Series I/O pin.
F
step
jitter
DDS
Figure 6
=
=
=
IN/OUT
1.728GHz
-------------------------
CRYSTAL
lists all the possible external clocks to PNX15xx Series. The definition of an
clk_lan
clk_lan
clk_gpio_14
clk_lan
clk_gpio_13
clk_gpio_q5
clk_fgpi
1.728GHz N
----------------------------------- -
-------------------------
1.728GHz
OUT
2
IN
IN
32
1
2
summarizes the assignment of the different DDSes of the PNX15xx
32
=
=
PIN I/O Name
XTAL_IN
PCI_SYS_CLK
PCI_CLK
Rev. 3 — 17 March 2006
0.4Hz
0.579ns
, where N is a 31-bit value stored in the DDS[8:0]_CTL MMIO
clk_qvcp_out
clk_qvcp_out
clk_lan
Description
27 MHz clock input from oscillator pad
Clock to off-chip PCI devices; note this signal may be
routed back into the PCI_CLK input pad.
External PCI module clock
ao_osclk
ao_osclk
Chapter 5: The Clock Module
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
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