pnx1500 NXP Semiconductors, pnx1500 Datasheet - Page 657

• Manufacturer Part Number: pnx1500
• Description: Pnx15xx Series Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
Table 5: VLD Command Register
PNX15XX_SER_3
Product data sheet
Name
Count
Command
Size
(Bits)
8
4
3.2.10 VLD Shift Register (VLD_SR)
3.2.11 VLD Quantizer Scale (VLD_QS)
3.2.12 VLD Picture Info (VLD_PI)
3.2.13 VLD Bit Count (VLD_BIT_CNT)
Description
For the ‘Shift Bitstream’ command, only the lower 4 bits are used; the upper 4 bits should be set to 0.
All 8 bits are used for the ‘Parse macroblocks’ and ‘Search for given start code’ commands.
Command code of the VLD command to be executed
3.3 VLD Operation
requested number of items have been processed. Note also that the expiration of a
DMA count does not constitute the completion of a command. When a DMA count
expires the VLD is stalled as it waits for a new DMA to be initiated. It is not halted.
The ‘Initialize VLD’ command initializes the VLD_BIT_CNT register (the bit counter)
to zero.
The ‘Search for the given start code’ command searches for the start code pattern
given in the COUNT field (in the least significant 8 bits) of the VLD_COMMAND
register. A valid MPEG-1/-2 start code is a 32-bit pattern with the upper 24-bits equal
to 0x000001. For each start code encountered in the bitstream, the 8-bits following
the 0x000001 pattern is compared against the given 8-bit start code pattern until a
perfect match is obtained. Once the given start-code is found, the VLD sets the
COMMAND_DONE bit in the VLD_MC_STATUS register. At that point, the VLD will
interrupt the CPU if the corresponding bit in the VLD_IE register is also set.
This read only register is a shadow of the VLD’s operational shift register and it allows
the CPU to access the bitstream through the VLD. Bits 0 through 15 are the current
contents of the VLD shift register. Bit 16 to 31 are RESERVED and should be treated
as undefined by the programmer.
This 5-bit register read/write register contains the quantization scale code to be
output by the VLD until it is overridden by a macroblock quantizer scale code. The
quantizer scale code is part of the macroblock header output.
This 32-bit read/write register contains the picture layer information necessary for the
VLD (and MC) to parse the macroblocks within that picture. Again, the values of each
of these fields are determined by the appropriate standard (MPEG-1 or MPEG-2)
The number of bits consumed by the VLD is updated in the VLD_BIT_CNT register.
VLD_BIT_CNT can be initialized to zero by issuing the ‘Initialize VLD’ command. It
counts upward when bits are shifted out and consumed by the VLD. This counter
wraps around after reaching the maximum value.
The normal mode of operation will be for the CPU to request the VLD to parse some
number of macroblocks. Once the VLD has begun parsing macroblocks it may stop
for any one of the following reasons:
Rev. 3 — 17 March 2006
Chapter 21: MPEG-1 and MPEG-2 Variable Length Decoder
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
21-9