pnx1500 NXP Semiconductors, pnx1500 Datasheet - Page 246

• Manufacturer Part Number: pnx1500
• Description: Pnx15xx Series Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
Table 8: Registers Description
PNX15XX_SER_3
Product data sheet
Bit
Offset 0x04 0024
31:21
20:0
Offset 0x04 0028
31:16
15:0
Offset 0x04 002C
31:0
Offset 0x04 0030
31:0
Offset 0x04 0034
31:0
Offset 0x04 0038
31:11
10
9
8
7:4
3:0
Offset 0x04 003C
31:16
Symbol
pci_base2_hi
Reserved
Unused
read_lifetime
gppm_addr
gppm_wdata
gppm_rdata
Reserved
gppm_done
init_pci_cycle
Reserved
gppm_cmd
gppm_ben
Reserved
PCI_Base2_hi
Read Data Lifetime Timer
General Purpose PCI Master (GPPM) Address
General Purpose PCI Master (GPPM) Write Data
General Purpose PCI Master (GPPM) Read Data
General Purpose PCI Master (GPPM) Control
Unlock Register
Acces
s
R/W
R
R/W
R/W
R/W
R
R
R
R/W
R
R/W
R/W
R
Value
0
0
-
8000
0
0
0
0
0
0
0
0
0
0
Rev. 3 — 17 March 2006
Description
For internal address decoding: high bar of second aperture for
external PCI access (up to but not including). This register affects
the decode and routing of the bus controllers. It should not be relied
on as stable for 10 clocks after writing. It is recommended the
PCI_Base2_lo be initialized before the PCI_Base2_hi to avoid a
potentially large segment of address space being temporarily
allocated to PCI space. The PCI_Base2 aperture may be declared
as a internal view of PCI IO space or as PCI memory space. See
pci_io register for more information.
This register is the amount of time (in PCI clocks) the PCI will hold a
piece of data exclusively for an external PCI master. The timer is
initiated when the PCI can not complete the requested read in 16
clock cycles and issues a retry.
This register will be written with the address for the single data
phase cycle to be issued on the PCI bus. It will accept only 32-bit
writes. When issuing type 0 configuration transactions, the device
number (bits [15:11]) is expanded to bits [31:11] on the PCI bus as
defined in the PCI 2.2 spec.
This register will be written with the data for the single data phase
cycle to be issued on the PCI bus. This register will accept any size
write.
This register will hold data from the selected target after completion
of the read.
1 = cycle has completed. This bit can also be viewed in the
gppm_status register. Write to register 0x40FC8 to clear.
1 = initiate a PCI single data phase transaction on the PCI bus with
address “gppm_addr” and data “gppm_data.”
Command to be used with PCI cycle. Acceptable commands to use
in the command field include IO read, IO write, memory Read,
memory Write, configuration read and interrupt acknowledge. If
configuration management is enabled, configuration write may be
used.
Byte enables to be used with PCI cycle
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Chapter 7: PCI-XIO Module
PNX15xx Series
7-27