xc5210 Xilinx Corp., xc5210 Datasheet - Page 30

• Manufacturer Part Number: xc5210
• Description: Logic Cell Array Family , Inc
• Manufacturer: Xilinx Corp.

XC5200 Logic Cell Array Family
Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from
benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating
conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the
XACT timing calculator and used in the simulator.
Note:
Description
Global Signal Distribution
Internal Clock to Output Pad Delay
From pad through global buffer, to any clock (CK)
From clock (CK) to output pad (fast), using direct connect
between Q and output (O)
From clock (CK) to output pad (slew-limited), using direct
connect between Q and output (O)
1.
Die-size-dependent parameters are based upon XC5210 characterization. Production specifications will vary with array
size.
26
Symbol
T
T
T
OKPOF
OKPOS
BUFG
Speed Grade
XC5202
XC5204
XC5206
XC5210
XC5215
XC5202
XC5204
XC5206
XC5210
XC5215
XC5202
XC5204
XC5206
XC5210
XC5215
Device
14.8
14.8
Max
(ns)
-6
9.4
9.4
9.9
9.9
12.7
12.7
Max
(ns)
-5
8.8
8.8
8.9
8.9
Preliminary
Max
(ns)
-4