xc5210 Xilinx Corp., xc5210 Datasheet - Page 18

• Manufacturer Part Number: xc5210
• Description: Logic Cell Array Family , Inc
• Manufacturer: Xilinx Corp.

XC5200 Logic Cell Array Family
General Routing Matrix
The General Routing Matrix, shown in Figure 11, provides
flexible bidirectional connections to the Local Interconnect
Matrix through a hierarchy of different-length metal
segments in both the horizontal and vertical directions. A
programmable interconnect point (PIP) establishes an
electrical connection between two wire segments. The
PIP, consisting of a pass transistor switch controlled by a
memory element, provides bidirectional (in some cases,
unidirectional) connection between two adjoining wires. A
collection of PIPs inside the General Routing Matrix and in
the Local Interconnect Matrix provides connectivity
between various types of metal segments. A hierarchy of
PIPs and associated routing segments combine to provide
a powerful interconnect hierarchy:
• Forty bidirectional single-length segments per CLB
• Sixteen bidirectional double-length segments per CLB
• Eight horizontal and eight vertical bidirectional Longline
• Two low-skew horizontal and vertical unidirectional
Single- and Double-Length Lines
The single- and double-length bidirectional line segments
make up the bulk of the routing channels. The double-
length lines hop across every other CLB to reduce the
propagation delays in speed-critical nets. Regenerating
the signal strength is recommended after traversing three
or four such segments. XACT place-and-route software
automatically connects buffers in the path of the signal as
necessary. Single- and double-length lines cannot drive
onto Longlines and global lines; Longlines and global lines
can, however, drive onto single- and double-length lines.
As a general rule, Longline and global-line connections to
the programmable routing matrix are unidirectional, with
the signal direction from these lines toward the routing
matrix.
Longlines
Longlines are used for high-fan-out signals, 3-state
busses, low-skew nets, and faraway destinations. Row
and column splitter PIPs in the middle of the array
effectively double the total number of Longlines by
electrically dividing them into two separated half-lines. The
horizontal Longlines are driven by the 3-state buffers in
provide ten routing channels to each of the four
neighboring CLBs in four directions.
provide four routing channels to each of four other (non-
neighboring) CLBs in four directions.
segments span the width and height of the chip,
respectively.
global-line segments span each row and column of the
chip, respectively.
14
each CLB, and are driven by similar buffers at the
periphery of the array from the VersaRing I/O Interface.
Bus-oriented microprocessor designs are accommodated
by using horizontal Longlines in conjunction with the 3-
state buffers in the CLB and in the VersaRing. Additionally,
programmable keeper cells at the periphery can be
enabled to retain the last valid logic level on the Longlines
when all buffers are in 3-state mode.
Longlines connect to the single-length or double-length
lines, or to the logic inside the CLB, through the General
Routing Matrix. The only manner in which a Longline can
be driven is through the four 3-state buffers; therefore, a
Longline-to-Longline or single-line-to-Longline connection
through PIPs in the General Routing Matrix is not
possible. Again, as a general rule, long- and global-line
connections
unidirectional, with the signal direction from these lines
toward the routing matrix.
The XC5200 family has no pull-ups on the ends of the
Longlines sourced by TBUFs. Consequently, wired
functions
multiplexing functions requiring pull-ups for undefined
states (i.e., bus applications) must be implemented in a
different way. In the case of the wired functions, the same
functionality can be achieved by taking advantage of the
carry/cascade logic described above, implementing a
wide logic function in place of the wired function. In the
case of 3-state bus applications, the user must insure that
all states of the multiplexing function are defined. This
process is as simple as adding an additional TBUF to
drive the bus High when the previously undefined states
are activated.
Global Clock Buffers
Global buffers in Xilinx FPGAs are special buffers that
drive a dedicated routing network called Global Lines, as
shown in Figure 12. This network is intended for high-fan-
out clocks or other control signals, to maximize speed and
minimize skewing while distributing the signal to many
loads.
The XC5200 family has a total of four global buffers
(BUFG symbol in the library), each with its own dedicated
routing channel. Two are distributed vertically and two
horizontally throughout the LCA.
(i.e.,
to
WAND
the
General
and
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Routing
Preliminary (v1.0)
Matrix
and
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are