xc5210 Xilinx Corp., xc5210 Datasheet - Page 27

• Manufacturer Part Number: xc5210
• Description: Logic Cell Array Family , Inc
• Manufacturer: Xilinx Corp.

Pin Descriptions
Permanently Dedicated Pins
V
Eight or more (depending on package type) connections
to the nominal +5-V supply voltage. All must be
connected.
GND
Eight or more (depending on package type) connections
to ground. All must be connected.
CCLK
During configuration, Configuration Clock is an output of
the LCA in master modes or Asynchronous Peripheral
mode, but is an input to the LCA in Slave Serial mode and
Synchronous Peripheral mode.
After configuration, CCLK has a weak pull-up resistor and
can be selected as Readback Clock.
DONE
This is a bidirectional signal with optional pull-up resistor.
As an output, it indicates the completion of the
configuration
determines the exact timing, the clock source for the Low-
to-High transition, and enable of the pull-up resistor.
As an input, a Low level on DONE can be configured to
delay the global logic initialization or the enabling of
outputs.
PROGRAM
This is an active-Low input, held Low during configuration,
that forces the LCA to clear its configuration memory.
When PROGRAM goes High, the LCA executes a
complete clear cycle, before it goes into a WAIT state and
releases INIT. After configuration, it has an optional pull-
up resistor.
cc
process.
The
configuration
program
23
User I/O Pins That Can Have Special Functions
RDY/BUSY
During peripheral modes, this pin indicates when it is
appropriate to write another byte of data into the LCA
device. The same status is also available on D7 in
Asynchronous Peripheral mode, if a read operation is
performed
configuration, this is a user-programmable I/O pin.
RCLK
During Master Parallel configuration, each change on the
A0-15 outputs is preceded by a rising edge on RCLK, a
redundant output signal. After configuration, this is a user-
programmable I/O pin.
M0, M1, M2
As mode inputs, these pins are sampled before the start of
configuration to determine the configuration mode to be
used.
After configuration, M0, M1, and M2 become user-
programmable I/O.
TDO
If boundary scan is used, this is the Test Data Output.
If boundary scan is not used, this pin becomes user-
programmable I/O.
TDI, TCK, TMS
If boundary scan is used, these pins are Test Data In, Test
Clock, and Test Mode Select inputs, respectively, coming
directly from the pads, bypassing the IOBs. These pins
can also be used as inputs to the CLB logic after
configuration is completed.
If the boundary scan option is not selected, all boundary
scan functions are inhibited once configuration is
completed. These pins become user-programmable I/O.
HDC
High
configuration is completed. It is available as a control
output indicating that configuration is not yet completed.
After configuration, this is a user-programmable I/O pin.
During
when
Configuration
the
device
is
is
driven
selected.
High
After
until
R