xc5210 Xilinx Corp., xc5210 Datasheet - Page 28

• Manufacturer Part Number: xc5210
• Description: Logic Cell Array Family , Inc
• Manufacturer: Xilinx Corp.

XC5200 Logic Cell Array Family
Pin Descriptions
LDC
Low During Configuration is driven Low until configuration
completes. It is available as a control output indicating that
configuration is not yet completed. After configuration, this
is a user-programmable I/O pin.
INIT
Before and during configuration, this is a bidirectional
signal. An external pull-up resistor is recommended.
As an active-Low open-drain output, INIT is held Low
during the power stabilization and internal clearing of the
configuration memory. As an active-Low input, it can be
used to hold the LCA device in the internal WAIT state
before the start of configuration. Master-mode devices
stay in a WAIT state an additional 30 to 300 s after INIT
has gone High.
During configuration, a Low on this output indicates that a
configuration data error has occurred. After configuration,
this is a user-programmable I/O pin.
GCK1 - GCK4
Four Global Inputs each drive a dedicated internal global
net with short delay and minimal skew. If not used for this
purpose, any of these pins is a user-programmable I/O
pin.
CS0, CS1, WS, RS
These four inputs are used in peripheral modes. The chip
is selected when CS0 is Low and CS1 is High. While the
chip is selected, a Low on Write Strobe (WS) loads the
data present on the D0 - D7 inputs into the internal data
buffer; a Low on Read Strobe (RS) changes D7 into a
status output: High if Ready, Low if Busy, and D0…D6 are
active Low. WS and RS should be mutually exclusive, but
if both are Low simultaneously, the Write Strobe overrides.
After configuration, these are user-programmable I/O
pins.
A0 - A17
During Master Parallel mode, these 18 output pins
address the configuration EPROM. After configuration,
these are user-programmable I/O pins.
Before and during configuration, all outputs that are not used for the configuration process are 3-stated with a
50-k to 100-k pull-up resistor.
24
D0 - D7
During Master Parallel and peripheral configuration
modes, these eight input pins receive configuration data.
After configuration, they are user-programmable I/O pins.
DIN
During Slave Serial or Master Serial configuration modes,
this is the serial configuration data input receiving data on
the rising edge of CCLK.
During parallel configuration modes, this is the D0 input.
After configuration, DIN is a user-programmable I/O pin.
DOUT
During configuration in any mode, this is the serial
configuration data output that can drive the DIN of daisy-
chained slave LCA devices. DOUT data changes on the
falling edge of CCLK, 1.5 CCLK periods after it was
received at the DIN input. After configuration, DOUT is a
user-programmable I/O pins.
Unrestricted User-Programmable I/O Pins
I/O
A pin that can be configured to be input and/or output after
configuration is completed. Before configuration is
completed, these pins have an internal high-value pull-up
resistor that defines the logical level as High.
Preliminary