dspb56011 Freescale Semiconductor, Inc, dspb56011 Datasheet - Page 80

• Manufacturer Part Number: dspb56011
• Description: 24-bit Dvd Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

Design Considerations
Host Port Considerations
DSP Programming Considerations
4-8
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command exception after the HC bit is cleared. For these reasons, the HV bits
must not be changed at the same time that the HC bit is cleared.
Variance in the Host Interface Timing—The Host Interface (HI) may vary
(e.g. due to the PLL lock time at reset). Therefore, a host which attempts to
load (bootstrap) the DSP should first make sure that the part has completed its
HI port programming (e.g., by setting the INIT bit in ICR then polling it and
waiting it to be cleared, then reading the ISR or by writing the TREQ/RREQ
together with the INIT and then polling INIT, ISR, and the HOREQ pin).
Synchronization of Status Bits from Host to DSP—DMA, HF1, HF0, and
HCP, HTDE, and HRDF status bits are set or cleared by the host processor
side of the interface. These bits are individually synchronized to the DSP
clock. (Refer to the User’s Manual for descriptions of these status bits.)
Reading HF0 and HF1 as an Encoded Pair—Care must be exercised when
reading status bits HF0 and HF1 as an encoded pair, (i.e., the four
combinations 00, 01, 10, and 11 each have significance). A very small
probability exists that the DSP will read the status bits synchronized during
transition. Therefore, HF0 and HF1 should be read twice and checked for
consensus.
DSP56011 Technical Data Sheet, Rev. 1
Preliminary Information
MOTOROLA