dspb56011 Freescale Semiconductor, Inc, dspb56011 Datasheet
dspb56011
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dspb56011 Summary of contents
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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Advance Information 24-BIT DVD DIGITAL SIGNAL PROCESSOR The DSP56011 is a high-performance programmable Digital Signal Processor (DSP) developed for Digital Versatile Disc (DVD), High-Definition Television (HDTV), and Advanced Set-top audio decoding. The DSP56011 is optimized with ...
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DSP56011 SECTION 1 SIGNAL/CONNECTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 1-1 SECTION 2 SPECIFICATIONS . . . . . . . . . . . . . ...
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FEATURES Digital Signal Processing Core • Efficient, object-code compatible, 24-bit DSP56000 family DSP engine – 47.5 Million Instructions Per Second (MIPS) with 21.05 ns instruction cycle at 95 MHz – Highly parallel instruction set with unique DSP addressing modes – ...
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DSP56011 Features Memory • Modified Harvard architecture allows simultaneous access to program and data memories • 12800 24-bit on-chip Program ROM • 4096 24-bit on-chip X-data RAM and 3584 24-bit on-chip X-data ROM • 4352 24-bit on-chip Y-data RAM and ...
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Peripheral and Support Circuits • SAI includes: – Two receivers and three transmitters – Master or slave capability 2 – Sony, and Matshushita audio protocol implementations – Two sets of SAI interrupt vectors • SHI features: – Single ...
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DSP56011 Documentation DOCUMENTATION Table 2 lists the documents that provide a complete description of the DSP56011 and are required to design properly with the part. Documentation is available from a local Motorola distributor, a Motorola semiconductor sales office, a Motorola ...
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SIGNAL/CONNECTION DESCRIPTIONS SIGNAL GROUPINGS The input and output signals of the DSP56011 are organized into ten functional groups, as shown in Table 1-1 and as illustrated in Figure 1-1 . Table 1-1 DSP56011 Functional Signal Groupings Functional Group Power (V ...
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Signal/Connection Descriptions Signal Groupings Power Inputs: V PLL CCP 4 V Internal Logic CCQ CCA CCD CCH 2 V SHI CCS Grounds: GND PLL P 4 GND Internal Logic Q 3 ...
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POWER Power Name V PLL Power—V CCP should be well-regulated and the input should be provided with an extremely low impedance path to the 0.1 F capacitor located as close as possible to the chip package. V ...
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Signal/Connection Descriptions Ground GROUND Ground Name GND PLL Ground—GND P provided with an extremely low-impedance path to ground. V bypassed to GND package. GND Internal Logic Ground—GND Q logic. This connection must be tied externally to all other chip ground ...
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PHASE LOCK LOOP (PLL) State During Signal Name Type PLOCK Output Indeterminate PCAP Input Input PINIT Input Input EXTAL Input Input MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 Table 1-4 Phase Lock Loop Signals Signal Description Reset Phase Locked—PLOCK is ...
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Signal/Connection Descriptions Interrupt and Mode Control INTERRUPT AND MODE CONTROL Table 1-5 Interrupt and Mode Control Signal State During Type Name Reset MODA Input Input (MODA) Mode Select A—This input signal has three functions: IRQA Input 1-6 DSP56011 Technical Data ...
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Table 1-5 Interrupt and Mode Control (Continued) Signal State During Type Name Reset MODB Input Input (MODB) Mode Select B—This input signal has two functions: IRQB Input MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 Signal Description • to work with ...
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Signal/Connection Descriptions Interrupt and Mode Control Table 1-5 Interrupt and Mode Control (Continued) Signal State During Type Name Reset MODC Input, edge- Input (MODC) Mode Select C—This input signal has two functions: triggered NMI Input, edge- triggered RESET Input Active ...
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HOST INTERFACE (HI) The HI provides a fast parallel data to 8-bit port, which may be connected directly to the host bus. The HI supports a variety of standard buses, and can be directly connected to a number of industry ...
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Signal/Connection Descriptions Host Interface (HI) Table 1-6 Host Interface (Continued) State During Signal Name Type HR/W Input Input PB11 Input/ Output HEN Input Input PB12 Input/ Output HOREQ Open- Input drain Output PB13 Input/ Output 1-10 DSP56011 Technical Data Sheet, ...
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Table 1-6 Host Interface (Continued) State During Signal Name Type HACK Input Input PB14 Input/ Output MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 Signal Description Reset Host Acknowledge—This input has two functions. It provides a host acknowledge handshake signal for ...
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Signal/Connection Descriptions Serial Host Interface (SHI) SERIAL HOST INTERFACE (SHI) The SHI has five I/O signals that can be configured to allow the SHI to operate in 2 either SPI mode. Table 1-7 Serial Host Interface (SHI) ...
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Table 1-7 Serial Host Interface (SHI) Signals (Continued) State Signal Signal during Name Type Reset MISO Input or Tri-stated Output SDA Input or open- drain Output MOSI Input or Tri-stated Output HA0 Input MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 ...
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Signal/Connection Descriptions Serial Host Interface (SHI) Table 1-7 Serial Host Interface (SHI) Signals (Continued) State Signal Signal during Name Type Reset SS Input Tri-stated HA2 Input HREQ Input or Tri-stated Output 1-14 DSP56011 Technical Data Sheet, Rev. 1 Signal Description ...
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SERIAL AUDIO INTERFACE (SAI) The SAI is composed of separate receiver and transmitter sections. SAI Receive Section The receive section of the SAI has four dedicated signals Table 1-8 Serial Audio Interface (SAI) Receive Signals State Signal Signal during Name ...
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Signal/Connection Descriptions Serial Audio Interface (SAI) SAI Transmit Section The transmit section of the SAI has five dedicated signals. Table 1-9 Serial Audio Interface (SAI) Transmit Signals State Signal Signal during Name Type Reset SDO0 Output Driven high SDO1 Output ...
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GENERAL PURPOSE INPUT/OUTPUT (GPIO) Table 1-10 General Purpose I/O (GPIO) Signals Signal Signal Type Name GPIO0– Input or GPIO7 Output (standard or open-drain) DIGITAL AUDIO INTERFACE (DAX) Table 1-11 Digital Audio Interface (DAX) Signals Signal Name Type ADO Output ACI ...
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Signal/Connection Descriptions OnCE Port OnCE PORT Table 1-12 On-Chip Emulation Port (OnCE) Signals State Signal Signal during Name Type Reset DSI Input Low Output OS0 Output DSCK Input Low Output OS1 Output 1-18 DSP56011 Technical Data Sheet, Rev. 1 Signal ...
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Table 1-12 On-Chip Emulation Port (OnCE) Signals (Continued) State Signal Signal during Name Type Reset DSO Output Pulled high DR Input Input MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 Signal Description Debug Serial Output—Data contained in one of the OnCE ...
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Signal/Connection Descriptions OnCE Port 1-20 DSP56011 Technical Data Sheet, Rev. 1 Preliminary Information MOTOROLA ...
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INTRODUCTION The DSP56011 is fabricated in high density CMOS with Transistor-Transistor Logic (TTL) compatible inputs and outputs. The DSP56011 specifications are preliminary and are from design simulations, and may not be fully tested or guaranteed at this early stage of ...
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Specifications Thermal characteristics 1 Rating Supply Voltage All input voltages Current drain per pin excluding V Operating temperature range Storage temperature Notes: 1. GND = 5 Absolute maximum ratings are stress ...
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DC ELECTRICAL CHARACTERISTICS Table 2-3 DC Electrical Characteristics Characteristics Supply voltage Input high voltage • EXTAL • RESET • MODA, MODB, MODC 1 • ACI, SHI inputs • All other inputs Input low voltage • EXTAL • MODA, MODB, MODC ...
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Specifications AC Electrical Characteristics AC ELECTRICAL CHARACTERISTICS The timing waveforms in the AC Electrical Characteristics are tested with a V maximum of 0.5 V and a V RESET, MODA, MODB, MODC, ACI, and SHI inputs (MOSI/HA0, SS/HA2, MISO/SDA, SCK/SCL, HREQ). ...
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EXTERNAL CLOCK OPERATION The DSP56011 system clock is externally supplied via the EXTAL pin. Timings shown in this document are valid for clock rise and fall times maximum. The 81 MHz speed allows the DSP56011 to take ...
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Specifications Phase Lock Loop (PLL) Characteristics PHASE LOCK LOOP (PLL) CHARACTERISTICS Table 2-6 Phase Lock Loop (PLL) Characteristics Characteristics VCO frequency when PLL enabled PLL external capacitor (PCAP pin CCP Note: Cpcap is the value of the ...
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Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing (Continued) No. Characteristics 22 Delay from General Purpose Output valid to interrupt request deassertion for level sensitive fast interrupts— if second interrupt instruction is: • Single cycle • Two cycles 25 ...
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Specifications RESET, Stop, Mode Select, and Interrupt Timing RESET MODA, MODB MODC Figure 2-3 Operating Mode Select Timing IRQA, IRQB, NMI IRQA, IRQB, NMI Figure 2-4 External Interrupt Timing (Negative-Edge Triggered) General Purpose I/O (Output) 18 IRQA IRQB NMI Figure ...
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HOST INTERFACE (HI) TIMING Note: Active low lines should be “pulled up” manner consistent with the AC and DC specifications. Table 2-8 Host I/O Timing (All Frequencies) Num Characteristics 31 HEN/HACK assertion width • CVR, ICR, ISR, RXL ...
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Specifications Host Interface (HI) Timing Table 2-8 Host I/O Timing (All Frequencies) (Continued) Num Characteristics 47 Delay from HEN deassertion to HOREQ assertion for 4,5 RXL read 48 Delay from HEN deassertion to HOREQ assertion for 4,5 TXL write 49 ...
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HOREQ (Output) RXH HEN Read (Input HA2–HA0 Address Valid (Input) 41 HR/W (Input H0–H7 Data (Output) Valid Figure 2-9 Host Read Cycle (Non-DMA Mode) HOREQ (Output) TXH HEN Write (Input HA2–HA0 Address Valid (Input) ...
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Specifications Host Interface (HI) Timing HOREQ (Output RXH HACK Read (Input Data H0–H7 Valid (Output) HOREQ (Output TXH HACK Write (Input) 33 H0–H7 Data (Output) Valid 2-12 DSP56011 Technical Data Sheet, Rev ...
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SERIAL AUDIO INTERFACE (SAI) TIMING) Table 2-9 Serial Audio Interface (SAI) Timing No. Characteristics 111 Minimum Serial Clock cycle = T (min) SAICC 112 Serial Clock high period 113 Serial Clock low period 114 Serial Clock rise/fall time 115 Data ...
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Specifications Serial Audio Interface (SAI) Timing) SCKR (RCKP = 1) SCKR (RCKP = 0) SDI0–SDI1 (Data Input) WSR (Input) WSR (Output) 2-14 DSP56011 Technical Data Sheet, Rev. 1 111 112 114 111 113 114 115 116 Valid 119 118 Valid ...
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SCKT (TCKP = 1) SCKT (TCKP = 0) SDO0–SDO2) (Data Output) WST (Input) WST (Output) MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 111 112 114 111 113 114 121 124 123 Valid Figure 2-14 SAI Transmitter Timing Preliminary Information Specifications ...
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Specifications Serial Host Interface (SHI) SPI Protocol Timing SERIAL HOST INTERFACE (SHI) SPI PROTOCOL TIMING Table 2-10 Serial Host Interface (SHI) SPI Protocol Timing No. Characteristics — Tolerable spike width on Clock or Data input 141 Minimum Serial Clock cycle ...
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Table 2-10 Serial Host Interface (SHI) SPI Protocol Timing (Continued) No. Characteristics 144 Serial Clock rise/fall time 146 SS assertion to first SCK edge CPHA = 0 CPHA = 1 147 Last SCK edge to SS not asserted CPHA = ...
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Specifications Serial Host Interface (SHI) SPI Protocol Timing Table 2-10 Serial Host Interface (SHI) SPI Protocol Timing (Continued) No. Characteristics 151 SS deassertion to data 4 tri-stated 152 SCK edge to data out valid (data out delay time) 2 CPHA ...
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Table 2-10 Serial Host Interface (SHI) SPI Protocol Timing (Continued) No. Characteristics 160 SS deassertion pulse width CPHA = 0 161 HREQ input assertion to first SCK edge 162 HREQ input deassertion to last SCK sampling edge (HREQ input setup ...
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Specifications Serial Host Interface (SHI) SPI Protocol Timing SS (Input) 142 SCK (CPOL = 0) (Output) SCK (CPOL = 1) (Output) 148 MISO (Input) MOSI (Output) 161 HREQ (Input) Figure 2-15 SPI Master Timing (CPHA = 0) 2-20 DSP56011 Technical ...
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SS (Input) 142 SCK (CPOL = 0) (Output) SCK (CPOL = 1) (Output) MISO (Input) MOSI (Output) 161 HREQ (Input) Figure 2-16 SPI Master Timing (CPHA = 1) MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 Serial Host Interface (SHI) SPI ...
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Specifications Serial Host Interface (SHI) SPI Protocol Timing SS (Input) SCK (CPOL = 0) (Input) 146 SCK (CPOL = 1) (Input) 154 150 MISO (Output) 148 MOSI (Input) HREQ (Output) Figure 2-17 SPI Slave Timing (CPHA = 0) 2-22 DSP56011 ...
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SS (Input) 142 SCK (CPOL = 0) (Input) 146 SCK (CPOL = 1) (Input) 152 150 MISO (Output) MOSI (Input) HREQ (Output) Figure 2-18 SPI Slave Timing (CPHA = 1) MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 Serial Host Interface ...
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Specifications Serial Host Interface (SHI) I2C Protocol Timing SERIAL HOST INTERFACE (SHI (min Table 2-11 SHI I No. Characteristics Tolerable spike width on SCL or SDA filters bypassed Narrow filters enabled Wide filters enabled ...
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Programming the Serial Clock The Programmed Serial Clock Cycle, t HDM0 and HRS bits of the HCKR (SHI Clock control Register). The expression for CCP where – HRS is the Prescaler Rate Select bit. ...
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Specifications Serial Host Interface (SHI) I2C Protocol Timing Considerations for Programming the SHI Clock Control Register (HCKR)—Clock Divide Ratio The master must generate a bus free time greater than T172 slave when operating with a DSP56011 SHI I Table 2-12 ...
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Table 2-13 SHI Improved I No. Characteristic Sym. — Tolerable spike width on SCL or SDA 171 SCL Serial Clock T SCL cycle 172 Bus free time T BUF 173 Start condition T SU;STA setup time 174 Start condition T ...
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Specifications Serial Host Interface (SHI) I2C Protocol Timing Table 2-13 SHI Improved I No. Characteristic Sym. 175 SCL low period T LOW 176 SCL high period T HIGH 177 SCL rise time T R Output Input 178 SCL fall time ...
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Table 2-13 SHI Improved I No. Characteristic Sym. 182 SCL low to data T VD;DAT output valid 183 Stop condition T SU;STO setup time 184 HREQ input deassertion to last SCL edge (HREQ in setup time) 186 First SCL sampling ...
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Specifications Serial Host Interface (SHI) I2C Protocol Timing Table 2-13 SHI Improved I No. Characteristic Sym. Notes pF and result ...
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GENERAL PURPOSE INPUT/OUTPUT (GPIO) TIMING No. Characteristics 201 EXTAL edge to GPIO output valid (GPIO output delay time) 202 EXTAL edge to GPIO output not valid (GPIO output hold time) 203 GPIO input valid to EXTAL Edge (GPIO input setup ...
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Specifications Digital Audio Transmitter (DAX) Timing DIGITAL AUDIO TRANSMITTER (DAX) TIMING Table 2-15 56011 Digital Audio Transmitter Timing No. Characteristic ACI Frequency (see Note) 220 ACI Period 221 ACI High Duration 222 ACI Low Duration 223 ACI Rising Edge to ...
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ON-CHIP EMULATION (OnCE ) TIMING No. Characteristics 230 DSCK low 231 DSCK high 232 DSCK cycle time 233 DR asserted to DSO (ACK) asserted 234 DSCK high to DSO valid 235 DSCK high to DSO invalid 236 DSI valid to ...
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Specifications On-Chip Emulation (OnCE ) Timing Table 2-16 OnCE Timing (Continued) No. Characteristics 250A DR assertion width to recover from Stop • Stable External Clock, OMR Bit • Stable External Clock, OMR Bit • ...
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DSCK (Input) DSO (Output) 236 DSI (Input) Note: High Impedance, external pull-down resistor Figure 2-24 DSP56011 OnCE Data I/O to Status Timing DSCK (Input) 234 DSO (Output) Note: High Impedance, external pull-down resistor Figure 2-25 DSP56011 OnCE Read Timing OS1 ...
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Specifications On-Chip Emulation (OnCE ) Timing EXTAL (Note 2) OS0–OS1 (Output) (Note 1) Note: 1. High Impedance, external pull-down resistor 2. Valid when the ratio between EXTAL frequency and clock frequency equals 1 Figure 2-27 DSP56011 OnCE EXTAL to Status ...
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DR (Input) DSO (Output) Figure 2-31 Asynchronous Recovery from Stop State MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 On-Chip Emulation (OnCE ) Timing 250 251 Preliminary Information Specifications AA0286 2-37 ...
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Specifications On-Chip Emulation (OnCE ) Timing 2-38 DSP56011 Technical Data Sheet, Rev. 1 Preliminary Information MOTOROLA ...
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PIN-OUT AND PACKAGE INFORMATION This sections provides information about the available packages for this product, including diagrams of the package pinouts and tables describing how the signals described in Section 1 are allocated. The DSP56011 is available in a 100-pin ...
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Packaging Pin-out and Package Information TQFP Package Description Top and bottom views of the TQFP package are shown in Figure 3-1 and Figure 3-2 with their pin-outs. 76 GPIO7 GPIO6 GND D GPIO5 GPIO4 V CCD GPIO3 GPIO2 GND D ...
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V 50 CCS MODC/NMI MODB/IRQB MODA/IRQA RESET MISO/SDA GND S SCK/SCL EXTAL V CCP PCAP GND P PINIT GND Q V CCQ PLOCK not connected not connected not connected ACI ADO V CCH GND H HOREQ/PB13 H0/PB0 26 Figure 3-2 ...
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Packaging Pin-out and Package Information Pin Pin # Signal Name # 1 not connected 26 2 not connected 27 3 GND not connected 29 5 not connected 30 6 H7/PB7 31 7 H6/PB6 32 8 GND 33 ...
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Pin Signal Name Signal Name # ACI 31 GPIO7 ADO DSCK 70 DSI 69 DSO 68 EXTAL 42 GND 3 A GND 91 A GND 96 A GND 78 D GND 84 HACK D GND 8 H ...
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Packaging Pin-out and Package Information 0 100 1 L VIEW 0. Figure 3-3 100-pin Thin Quad Flat Pack (TQFP) Mechanical Information 3-6 DSP56011 Technical ...
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ORDERING DRAWINGS Complete mechanical information regarding DSP56011 packaging is available by facsimile through Motorola's Mfax™ system. Call the following number to obtain information by facsimile: The Mfax automated system requests the following information: • The receiving facsimile telephone number including ...
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Packaging Ordering Drawings 3-8 DSP56011 Technical Data Sheet, Rev. 1 Preliminary Information MOTOROLA ...
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DESIGN CONSIDERATIONS THERMAL DESIGN CONSIDERATIONS An estimation of the chip junction temperature, T equation: Equation Where ambient temperature ˚ package junction-to-ambient thermal resistance ˚C power dissipation ...
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Design Considerations Thermal Design Considerations The thermal performance of plastic packages is more dependent on the temperature of the printed circuit board to which the package is mounted. Again, if the estimations obtained from R performance is adequate, a system ...
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ELECTRICAL DESIGN CONSIDERATIONS This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. ...
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Design Considerations Power Consumption Considerations POWER CONSUMPTION CONSIDERATIONS Power dissipation is a key issue in portable DSP applications. Some of the factors which affect current consumption are described in this section. Most of the current consumed by CMOS devices is ...
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Current consumption test code: org p:RESET jmp org movep move move move move move nop rep move rep mov clr move rep mac move jmp TP1 nop jmp MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 Power Consumption Considerations MAIN p:MAIN ...
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Design Considerations Power-Up Considerations POWER-UP CONSIDERATIONS To power-up the device properly, ensure that the following conditions are met: • Stable power is applied to the device according to the specifications in Table 2-3 (DC Electrical Characteristics). • The external clock ...
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HOST PORT CONSIDERATIONS Careful synchronization is required when reading multi-bit registers that are written by another asynchronous system. This is a common problem when two asynchronous systems are connected. The situation exists in the Host Interface. The following paragraphs present ...
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Design Considerations Host Port Considerations command exception after the HC bit is cleared. For these reasons, the HV bits must not be changed at the same time that the HC bit is cleared. • Variance in the Host Interface Timing—The ...
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... DSPB56011 5 V Note: The DSPA56011 and the DSPB56011 include factory-programmed ROM containing support for Dolby AC- 3 with DVD specifications. These parts can be used only be customers licensed for Dolby AC-3. Future products in the DSP56011 family will include other ROM-based options. For additional information on future part development request customer-specific ROM-based support, call your local Motorola Semiconductor sales office or authorized distributor ...
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OnCE, Mfax, and Symphony are trademarks of Motorola, Inc. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, ...