dspb56011 Freescale Semiconductor, Inc, dspb56011 Datasheet - Page 45

• Manufacturer Part Number: dspb56011
• Description: 24-bit Dvd Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
Notes:
No.
160 SS deassertion pulse
161 HREQ input assertion to
162 HREQ input deassertion
163 First SCK edge to HREQ
width
CPHA = 0
first SCK edge
to last SCK sampling
edge (HREQ input setup
time) CPHA = 1
input not asserted
(HREQ input hold time)
1.
2.
3.
4.
Characteristics
For an internal clock frequency below 33 MHz, the minimum permissible internal clock to SCK frequency
ratio is 4:1.
For an internal clock frequency above 33 MHz, the minimum permissible internal clock to SCK frequency
ratio is 6:1.
In CPHA = 1 mode, the SPI slave supports data transfers at T
HTX is written at least T
supports data transfers at T
the first edge of SCK of each word.
When CPHA = 1, the SS line may remain active low between successive transfers.
Periodically sampled, not 100% tested
Table 2-10 Serial Host Interface (SHI) SPI Protocol Timing (Continued)
DSP56011 Technical Data Sheet, Rev. 1
Master
Master
Master
Mode
Slave
C
ns before the first edge of SCK of each word.In CPHA = 1 mode, the SPI slave
sPICC
Preliminary Information
= 3
Mode
Filter
T
C
, if the user assures that the HTX is written at least T
Serial Host Interface (SHI) SPI Protocol Timing
0.5
Expression
2
T
C
T
T
0
0
+ 4
SPICC
C
+ 6
SPICC
+
= 3
Min Max Min Max
16.3
67.7
81 MHz
0
0
T
C
, if the user assures that the
—
—
—
—
14.5
58.5
95 MHz
0
0
Specifications
—
—
—
—
C
ns before
Unit
2-19
ns
ns
ns
ns