dspb56011 Freescale Semiconductor, Inc, dspb56011 Datasheet - Page 14

• Manufacturer Part Number: dspb56011
• Description: 24-bit Dvd Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

Signal/Connection Descriptions
Interrupt and Mode Control
1-8
MODC
NMI
RESET
Signal
Name
Input, edge-
Input, edge-
triggered
triggered
Input
Type
Table 1-5 Interrupt and Mode Control (Continued)
Active
DSP56011 Technical Data Sheet, Rev. 1
Input (MODC) Mode Select C—This input signal has two functions:
State During
Reset
Preliminary Information
MODC is read and internally latched in the DSP when the
processor exits the Reset state. The logic state present on the
MODA, MODB, and MODC pins selects the initial DSP
operating mode. Several clock cycles after leaving the Reset
state, the MODC signal changes to the Non-Maskable
Interrupt request, NMI. The DSP operating mode can be
changed by software after reset.
Non-Maskable Interrupt Request—The NMI input is a
negative-edge triggered external interrupt request. This is a
level 3 interrupt that can not be masked out. Triggering
occurs at a voltage level and is not directly related to the fall
time of the interrupt signal. However, as the fall time of the
interrupt signal increases, the probability that noise on NMI
will generate multiple interrupts also increases. Hardware
reset causes this input to function as MODC.
Reset—This input causes a direct hardware reset of the
processor. When RESET is asserted, the DSP is initialized and
placed in the Reset state. A Schmitt-trigger input is used for
noise immunity. When the reset signal is deasserted, the initial
DSP operating mode is latched from the MODA, MODB, and
MODC signals. The DSP also samples the PINIT signal and
writes its status into the PEN bit of the PLL Control Register.
When the DSP comes out of the Reset state, deassertion
occurs at a voltage level and is not directly related to the rise
time of the RESET signal. However, the probability that
noise on RESET will generate multiple resets increases with
increasing rise time of the RESET signal.
For proper hardware reset to occur, the clock must be active,
since a number of clock ticks are required for proper
propagation of the hardware Reset state.
•
•
to work with the MODA and MODB signals to
select the DSP’s initial operating mode, and
to allow an external device to request a DSP
interrupt after internal synchronization.
Signal Description
MOTOROLA