dspb56011 Freescale Semiconductor, Inc, dspb56011 Datasheet - Page 51

• Manufacturer Part Number: dspb56011
• Description: 24-bit Dvd Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

Programming the Serial Clock
MOTOROLA
The Programmed Serial Clock Cycle, t
HDM0 and HRS bits of the HCKR (SHI Clock control Register).
The expression for t
In I
The DSP56011 provides an improved I
100 kHz I
kHz. The actual maximum frequency is limited by the bus capacitances (C
up resistors (R
on page 2-26), and by the input filters.
2
C mode, you may select a value for the Programmed Serial Clock Cycle from:
where
–
–
–
2
C bus protocol, the SHI in I
t
HRS is the Prescaler Rate Select bit. When HRS is cleared, the fixed divide-
by-eight prescaler is operational. When HRS is set, the prescaler is
bypassed.
MDM5–HDM0 are the Divider Modulus Select bits.
A divide ratio from 1 to 64 (HDM5–HDM0 = 0 to $3F) may be selected.
6
1024
I
2
DSP56011 Technical Data Sheet, Rev. 1
CCP
P
), (which affect the rise and fall time of SDA and SCL, see Table 2-12
T
C
= [T
(if HDM[5:0] = $02 and HRS = 1)
T
I
C
2
CCP
C
Preliminary Information
(if HDM[5:0] = $3F and HRS = 0)
is:
2
(HDM[5:0] + 1)
to
2
I
2
C mode supports data transfers at up to 1000
2
CCP
C bus protocol. In addition to supporting the
Serial Host Interface (SHI) I2C Protocol Timing
, is specified by the value of the HDM5–
(7
(1 – HRS) + 1)]
Specifications
L
),the pull-
2-25