adc16dv160cilq National Semiconductor Corporation, adc16dv160cilq Datasheet - Page 26

• Manufacturer Part Number: adc16dv160cilq
• Description: Dual Channel, 16-bit, 160 Msps Analog-to-digital Converter With Ddr Lvds Outputs
• Manufacturer: National Semiconductor Corporation

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10.0 SAMPLING EDGE
The internal clock divider features allows more flexible design
from the perspective of the system clocking scheme. The
ADC16DV160 supports divide by 1 or 2 clocking. This feature
may cause a potential issue when synchronizing the sample
edge of multiple ADCs when the internal clock is divided by 2
from the input clock (CLKIN). The ADC16DV160 samples the
analog input signal at the falling edge of the input clock, which
will be the falling edge of the internally divided by 2 clock when
divide by 2 is configured as shown as dashed lines in
FIGURE 17. State Machine Generating Fixed Pattern Sequence
FIGURE 19. Sampling Edge of Multiple ADCs with
FIGURE 18. Fixed Pattern at ADC Output with
Default SPI Register Values
Internal Division On
Figure
26
19
nals and/or input clock between multiple ADCs with this clock-
ing configuration, the sampling edge of some ADC, which is
ADC SLAVE I for this example, could be out of phase com-
pared to the ADC MASTER as shown in
sampling edge of the non-synchronized ADC can be syn-
chronized if the internal clock can be inverted through some
control bit. This sampling edge flipping function is provided by
the ADC16DV160 via SPI. See the SPI Register Map below
for the details.
below. If there is some timing skew of the SPI control sig-
30101454
30101455
30101456
Figure
19. The