adc16dv160cilq National Semiconductor Corporation, adc16dv160cilq Datasheet - Page 24

• Manufacturer Part Number: adc16dv160cilq
• Description: Dual Channel, 16-bit, 160 Msps Analog-to-digital Converter With Ddr Lvds Outputs
• Manufacturer: National Semiconductor Corporation

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of their bodies beside each other. For instance, place trans-
formers for the analog input and the clock input at 90° to one
another to avoid magnetic coupling. It is recommended to
place the transformers of the input signal path on the top side,
and the transformer for the clock signal path on the bottom
side. Every critical analog signal path like analog inputs and
clock inputs must be treated as a transmission line and should
have a solid ground return path with a small loop area.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any ex-
ternal component (e.g., a filter capacitor) connected between
the converter’s input pins and ground or to the reference pins
and ground should be connected to a very clean point in the
ground plane.
All analog circuitry (input amplifiers, filters, reference compo-
nents, etc.) should be placed in the analog area of the board.
All digital circuitry and dynamic I/O lines should be placed in
the digital area of the board. The ADC16DV160 should be
between these two areas. Furthermore, all components in the
reference circuitry and the input signal chain that are con-
nected to ground should be connected together with short
traces and enter the ground plane at a single, quiet point. All
ground connections should have a low inductance path to
ground.
The ground return current path can be well managed when
the supply current path is precisely controlled and the ground
layer is continuous and placed next to the supply layer. This
is because of the proximity effect. A ground return current
path with a large loop area will cause electro-magnetic cou-
pling and results in poor noise performance. Note that even if
there is a large plane for a current path, the high-frequency
return current path is not spread evenly over the large plane,
but only takes the path with lowest impedance. Instead of a
large plane, using a thick trace for supplies makes it easy to
control the return current path. It is recommended to place the
supply next to the GND layer with a thin dielectric for a smaller
ground return loop. Proper location and size of decoupling
capacitors provides a short and clean return current path.
7.0 SUPPLIES AND THEIR SEQUENCE
There are three supplies for the ADC16DV160: one 3.0V sup-
ply V
A3.0
and two 1.8V supplies V
A1.8
FIGURE 14. Serial Interface Protocol (Write Operation)
and V
DR
. It is recom-
24
mended to separate V
from V
cause lower SFDR and noise performance. When V
V
can be mitigated by adding a ferrite-bead on the V
path.
Different decoupling capacitors can be used to provide cur-
rent over wide frequency range. The decoupling capacitors
should be located close to the point of entry and close to the
supply pins with minimal trace length. A single ground plane
is recommended because separating ground under the
ADC16DV160 could cause an unexpected long return current
path.
The V
a diode turn-on voltage level. If this supply sequence is re-
versed, an excessive amount of current will flow through the
V
less than 60 V/mS (i.e., 60 μS for 3.0V supply) in order to
prevent excessive surge current through ESD protection de-
vices.
8.0 SERIAL CONTROL INTERFACE
The ADC16DV160 has a serial control interface that allows
access to the control registers. The serial interface is a gener-
ic 3-wire synchronous interface that is compatible with SPI-
type interfaces that are used on many microcontrollers and
DSP controllers. Each serial interface access cycle is exactly
16 bits long. A register-read or register-write can be accom-
plished in one cycle. Register space supported by this inter-
face is 64.
used by this interface. Each signal’s function is described be-
low. The SPI must be in a static condition during the normal
operation of the ADC16DV160, otherwise the performance of
the ADC16DV160 may degrade due to the coupling noise
generated by the SPI control signals. When a SPI bus is used
for multiple devices on the board, it is recommended to reduce
the potential for noise coupling by placing logic buffers be-
tween the SPI bus and the ADC16DV160.
DR
A3.0
are both from the same supply source, coupling noise
supply. The ramp rate of the V
A3.0
DR
to the rest of the supplies and analog signals could
supply must turn on before V
Figure 14
and
DR
Figure 15
from V
A1.8
show the access protocol
A3.0
A1.8
supplies, any coupling
supply must be kept
and/or V
30101451
DR
DR
reaches
A1.8
supply
and