adc16dv160cilq National Semiconductor Corporation, adc16dv160cilq Datasheet - Page 11

• Manufacturer Part Number: adc16dv160cilq
• Description: Dual Channel, 16-bit, 160 Msps Analog-to-digital Converter With Ddr Lvds Outputs
• Manufacturer: National Semiconductor Corporation

Specification Definitions
APERTURE DELAY is the time after the falling edge of the
clock to when the input signal is acquired or held for conver-
sion.
APERTURE JITTER (APERTURE UNCERTAINTY) is the
variation in aperture delay from sample to sample. Aperture
jitter manifests itself as noise in the output.
CLOCK DUTY CYCLE is the ratio of the time during one cycle
that a repetitive digital waveform is high to the total time of
one period. The specification here refers to the ADC clock
input signal.
COMMON MODE VOLTAGE (V
age applied to both input terminals of the ADC.
CONVERSION LATENCY is the number of clock cycles be-
tween initiation of conversion and the time when data is
presented to the output driver stage. Data for any given sam-
ple is available at the output pins the Pipeline Delay plus the
Output Delay after the sample is taken. New data is available
at every clock cycle, but the data lags the conversion by the
pipeline delay.
CROSSTALK is the coupling of energy from one channel into
the other channel.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input.
GAIN ERROR is the deviation from the ideal slope of the
transfer function. It can be calculated as:
It can also be expressed as Positive Gain Error and Negative
Gain Error, which are calculated as:
INTEGRAL NON LINEARITY (INL) is a measure of the de-
viation of each individual code from a best fit straight line. The
deviation of any given code from this straight line is measured
from the center of that code value.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
It is defined as the ratio of the power in the intermodulation
products to the total power in the original frequencies. IMD is
usually expressed in dBFS.
LSB (LEAST SIGNIFICANT BIT) is the bit that has the small-
est value or weight of all bits. This value is V
“V
lution in bits.
MISSING CODES are those output codes that will never ap-
pear at the ADC outputs. The ADC16DV160 is guaranteed
not to have any missing codes.
Gain Error = Positive Full Scale Error − Negative Full Scale
FS
” is the full scale input voltage and “n” is the ADC reso-
NGE = Offset Error - Negative Full Scale Error
PGE = Positive Full Scale Error - Offset Error
Error
CM
) is the common DC volt-
FS
/2
n
, where
11
MSB (MOST SIGNIFICANT BIT) is the bit that has the largest
value or weight. Its value is one half of full scale.
NEGATIVE FULL SCALE ERROR is the difference between
the actual first code transition and its ideal value of ½ LSB
above negative full scale.
OFFSET ERROR is the difference between the two input
voltages (V
32767LSB and 32768LSB with offset binary data format.
PIPELINE DELAY (LATENCY) See CONVERSION LATEN-
CY.
POSITIVE FULL SCALE ERROR is the difference between
the actual last code transition and its ideal value of 1½ LSB
below positive full scale.
POWER SUPPLY REJECTION RATIO is a measure of how
well the ADC rejects a change in the power supply voltage.
PSRR is the ratio of the Full-Scale output of the ADC with the
supply at the minimum DC supply limit to the Full-Scale output
of the ADC with the supply at the maximum DC supply limit,
expressed in dB.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the power of input signal to the total power of all other
spectral components below one-half the sampling frequency,
not including harmonics and DC.
SIGNAL TO NOISE AND DISTORTION (SINAD) Is the ratio,
expressed in dB, of the power of the input signal to the total
power of all of the other spectral components below half the
clock frequency, including harmonics but excluding DC.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-
ence, expressed in dB, between the power of input signal and
the peak spurious signal power, where a spurious signal is
any signal present in the output spectrum that is not present
at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-
pressed in dB, of the total power of the first eight harmonics
to the input signal power. THD is calculated as:
where f
through f
output spectrum.
SECOND HARMONIC DISTORTION (2
the difference expressed in dB, from the power of its 2
monic level to the power of the input signal.
THIRD HARMONIC DISTORTION (3
difference expressed in dB, from the power of the 3
monic level to the power of the input signal.
1
2
9
2
is the power of the fundamental frequency and f
IN+
are the powers of the first eight harmonics in the
– V
IN-
) required to cause a transition from code
RD
HARM or H3) is the
ND
HARM or H2) is
www.national.com
nd
rd
har-
har-
2
2