adc16dv160cilq National Semiconductor Corporation, adc16dv160cilq Datasheet - Page 20

• Manufacturer Part Number: adc16dv160cilq
• Description: Dual Channel, 16-bit, 160 Msps Analog-to-digital Converter With Ddr Lvds Outputs
• Manufacturer: National Semiconductor Corporation

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3.0 CLOCK INPUT CONSIDERATIONS
Clock Input Modes
The ADC16DV160 provides a low additive jitter differential
clock receiver for optimal dynamic performance over a wide
input frequency range. The input common mode of the clock
receiver is internally biased at V
as shown in
be AC-coupled. It is possible to DC-couple the clock input, but
the common mode (average voltage of CLK+ and CLK-) must
not be higher than V
reduction leading to lowered jitter performance. CLK+ and
CLK- should never be lower than AGND. A high speed back-
to-back diode connected between CLK+ and CLK- can limit
the maximum swing, but this could cause signal integrity con-
cerns when the diode turns on and reduces the load
impedance instantaneously.
The preferred differential transformer coupled clocking ap-
proach is shown in
on the center tap of the secondary of a flux type transformer
stabilizes clock input common mode. Differential clocking in-
creases the maximum amplitude of the clock input at the pins
6dB vs. the singled-ended circuit shown in
Figure
9. Normally the external clock input should
Figure
A1.8
/2 to prevent substantial tail current
10. A 0.1 μF decoupling capacitor
A1.8
/2 through a 10 kΩ resistor
FIGURE 8. Simulated ADC16DV160 Input S11
Figure
11. The
20
clock amplitude is recommended to be as large as possible
while CLK+ and CLK- both never exceed the supply rails of
V
ferential clock receiver shown in
amplitude at CLK+ and CLK- pins increases its slope around
the zero-crossing point so that higher signal-to-noise results.
A1.8
and AGND. With the equivalent input noise of the dif-
Figure
9, a larger clock
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