adc16dv160cilq National Semiconductor Corporation, adc16dv160cilq Datasheet
adc16dv160cilq
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adc16dv160cilq Summary of contents
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... Dual Supplies: 1.8V and 3.0V operation ■ Selectable input range: 2.4, 2.0, 1.5 and 1.0V ■ Sampling edge flipping with clock divider by 2 option ■ Internal clock divide © 2010 National Semiconductor Corporation ADC16DV160 ■ On-chip low jitter duty-cycle stabilizer ■ Power-down and sleep modes ■ ...
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Block Diagram www.national.com Functional Block Diagram 2 30101402 ...
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... Connection Diagram Ordering Information ≤ Industrial (−40°C +85°C) ADC16DV160CILQ ADC16DV160EB Pin-Out of ADC16DV160 Package 68–pin LLP Evaluation Board 3 30101401 www.national.com ...
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Pin Descriptions Pin(s) Name ANALOG IN− IN− RPI 10 RPQ RNI 12 RNQ V 2 RMI 16 V RMQ ...
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Pin(s) Name D1/0+/- D15/14+/- D1/0+/-I to D15/14+/-I 44, 45 OUTCLK+/- POWER SUPPLIES V 4, 14, 22 15, 18, 21, AGND 65 ...
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Absolute Maximum Ratings 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V ) A3.0 Supply Voltage ( A1.8 DR Voltage at any Pin except ...
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Dynamic Converter Electrical Characteristics Unless otherwise specified, the following specifications apply 160 MSPS at 2 -1dBFS, LVDS R CLK PP IN apply for All other limits apply ...
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Symbol Parameter +I Output Short Circuit Source Current SC −I Output Short Circuit Source Current SC LVDS Electrical Characteristics Unless otherwise specified, the following specifications apply 160 MSPS at 2 -1dBFS, LVDS R ...
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Symbol Parameter t CSB Setup Time CSS t CSB Hold Time CSH t Inter-access Gap IAG Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is ...
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FIGURE 2. SPI Write Timing FIGURE 3. SPI Read Timing 10 30101412 30101413 ...
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Specification Definitions APERTURE DELAY is the time after the falling edge of the clock to when the input signal is acquired or held for conver- sion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. ...
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Typical Performance Characteristics, DNL, INL Unless otherwise noted, these specifications apply: V Offset Binary Format. LVDS Rterm = 100 Ω. C DNL DNL vs.V www.national.com = +3.0V A3.0 A1 pF. Typical values are at T ...
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Typical Performance Characteristics, Dynamic Performance Unless otherwise noted, these specifications apply: V Offset Binary Format. LVDS Rterm = 100 Ω. C SNR, SINAD, SFDR vs. f SNR, SINAD, SFDR vs +3.0V 1.8V, f A3.0 ...
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SNR, SINAD, SFDR vs. V SNR, SFDR vs. Input Amplitude (dBFS) Spectral Response @ 10.1 MHz www.national.com A1.8 30101425 SNR, SFDR vs. Input Amplitude (dBc) 30101471 Spectral Response @ 32.5 MHz 30101461 14 DISTORTION vs. V A1.8 30101426 30101472 30101462 ...
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Spectral Response at 70 MHz Spectral Response @ 197 MHz Spectral Response @ 197 MHz, -7dBFS Spectral Response @ 150 MHz 30101463 Spectral Response @ 220 MHz 30101465 Two Tone Spectral Response @ 197 MHz, 203 MHz 30101467 15 30101464 ...
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Core Power vs. Temperature (Excludes I www.national.com ) DR 30101427 16 ...
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Functional Description Operating on dual +1.8V and +3.0V supplies, the AD- C16DV160 digitizes a differential analog input signal to 16 bits, using a differential pipelined architecture with error cor- rection circuitry and an on-chip sample-and-hold circuit to ensure maximum performance. ...
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Input Common Mode The analog inputs of the ADC16DV160 are not internally dc biased and the range of input common mode is very narrow. Hence it is highly recommended to use the common mode voltage (V , typically 1.15V) as ...
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The simulated S11 of the input circuit of the ADC16DV160 is shown in Figure 8. (Measured data will be provided in a future datasheet revision. Note that the simulated S11 normally closely matches the measured S11 500 MHz, ...
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CLOCK INPUT CONSIDERATIONS Clock Input Modes The ADC16DV160 provides a low additive jitter differential clock receiver for optimal dynamic performance over a wide input frequency range. The input common mode of the clock receiver is internally biased at V ...
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FIGURE 9. Equivalent Clock Receiver The differential receiver of the ADC16DV160 has an extreme- ly low-noise floor but its bandwidth is also extremely wide. The wide band clock noise folds back into the first Nyquist zone at the ADC output. ...
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CALIBRATION The automatic calibration engine contained within the AD- C16DV160 improves dynamic performance and reduces its part-to-part variation. Digital output signals including output clock (OUTCLK+/-) are all logic low while calibrating. The AD- C16DV160 is automatically calibrated when the ...
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FIGURE 13. Internal References and their Decoupling Reference Decoupling It is highly recommended to place the external decoupling capacitors connected and the pins as possible. The external decoupling capacitors ...
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For instance, place trans- formers for the analog input and the clock input at 90° to one another to avoid magnetic coupling recommended to place the transformers of the input signal path ...
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FIGURE 15. Serial Interface Protocol (Read Operation) Signal Descriptions SCLK: Used to register the input date (SDI) on the rising edge; and to source the output data (SDO) on the falling edge. User may disable clock and hold it in ...
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FIGURE 17. State Machine Generating Fixed Pattern Sequence 10.0 SAMPLING EDGE The internal clock divider features allows more flexible design from the perspective of the system clocking scheme. The ADC16DV160 supports divide clocking. This feature may ...
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Register Map Note: Accessing unspecified addresses may cause functional failure or damage. All reserved bits must be written with the listed default values. Operation Mode Operation Mode Bit 7 Data Format 1 0 Bits (6:5) Operation ...
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Fixed Pattern Mode: SEQ0 and SEQ1 7 6 SEQ1<2> SEQ1<1> Bits (7:5) 3 bits pattern code for SEQ3. 010 is the default. Bits (5:3) 3 bits pattern code for SEQ2. 010 is the default. Bit 1 Reserved, Must be set ...
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Fixed Pattern Mode: LSB PATTERN <111> D<7> D<6> D<5> Bits (7:5) 8 LSBs of a fixed pattern for Sequence >111> All '0' for default. Fixed Pattern Mode: MSB PATTERN <1110> D<7> D<6> D<5> Bits (7:5) 8 ...
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... Physical Dimensions www.national.com inches (millimeters) unless otherwise noted 68-Lead LLP Package Ordering Number ADC16DV160CILQ NS Package Number LQA68A 30 ...
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Notes 31 www.national.com ...
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... National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. ...